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1. 发明专利

JPH05327757A MONITOR CELL INSERTION CONTROL SYSTEM 失效
公开(公告)号：JPH05327757A
公开(公告)日：1993-12-10
申请号：JP13481792
申请日：1992-05-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： YAMASHITA HARUO , KAWAI MASAAKI , KOYANAGI TOSHINORI , KONDO RYUICHI , WAKIZAKA TAKAAKI , SUDO TOSHIYUKI , SATO HIROYUKI , UEDA HIROMI , AKUTSU KENJI , YASUDA TORU , MIYAMOTO AKIHIRO , ASHI MASAHIRO , SAITO KIYOSHI
IPC分类号： H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To insert a monitor cell at a designed position and to facilitate even the monitor of a duplex constitution in regard of a monitor cell insertion control system which monitors the inside of a cell processor. CONSTITUTION:A monitor cell inserting cell generating part 1 is provided together with a monitor cell inserting part 2, and a monitor cell extracting part 3. A monitor cell inserting cell is formed in a user cell train at the part 1. In a duplex constitution of 0 and 1 systems, the monitor cell inserting cells are formed in the same timing in both 0 and 1 systems. The part 2 detects the monitor cell inserting cell through a detecting part 6 and controls a selector 5. Then the part 2 selects and outputs the monitor cells held in a buffer memory 4 in order to insert and transfer the monitor cells. The part 3 extracts these monitor cells and collates them with each other to monitor the normal state of a transfer path.

2. 发明专利

JPH08331142A VIRTUAL PATH SWITCHING SYSTEM 失效
公开(公告)号：JPH08331142A
公开(公告)日：1996-12-13
申请号：JP13531495
申请日：1995-06-01
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： KOYANAGI TOSHINORI , IGUCHI KAZUO , OTA HIROSHI , UEMATSU HITOSHI , UEDA HIROMI , ASHI MASAHIRO , NAKANO YUKIO , TAKATORI MASAHIRO
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/70 , H04L12/709 , H04L12/713 , H04Q3/00
摘要： PURPOSE: To perform switching from a current virtual path to a standby virtual path. CONSTITUTION: A cell for switching is inserted to the same positions of the current virtual path and the standby virtual path by a transmitter 20, and a cell for switching control on either side of the current virtual path or the standby virtual path is detected by a receiver 30. The cell on one side is stored in a phase absorption buffer 48, and the cell for switching control on the path on the other side is detected, and the cell string of the current virtual path is switched to the one of the standby path read out or transmitted from the phase absorption buffer 48.

3. 发明专利

JPH0662036A SYNCHRONIZATION MAINTENANCE CONTROL SYSTEM 失效
公开(公告)号：JPH0662036A
公开(公告)日：1994-03-04
申请号：JP20872592
申请日：1992-08-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYANAGI TOSHINORI , OTA SHINJI , YAMASHITA HARUO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To maintain a synchronizing status for simultaneously reading identical effective cells from buffers even when there are the variation of transmission delay and the insertion of special cells, etc., concerning, to a synchronization maintenance control system for maintaining the synchronizing status of the effective cells of both systems. CONSTITUTION:This system is provided with the buffers (FIFO) 1 and 2 of '0' system and '1' system, a synchronization control part 3 for controlling the buffer 1 and 2 by read control signals and a selector 4 for switching between the '0' system and the '1' system by system selection control signals. In the synchronizing status capable of simultaneously reading the identical valid cells from the buffers 1 and 2, when the buffer of one system is turned free due to the transmission delay of the system, the read of the buffer of the other system is stopped and free cells are transmitted to the both systems. Then, when the effective cell arrives at the free buffer, the read of both the buffer of one system and the buffer of the other system is restarted and the synchronizing status is maintained.

4. 发明专利

JPH05227196A CONTINUOUS DUPLEX SWITCHING DEVICE 失效
公开(公告)号：JPH05227196A
公开(公告)日：1993-09-03
申请号：JP5691592
申请日：1992-02-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYANAGI TOSHINORI , OTA SHINJI , FUKUDA SETSU , OTA HIROSHI , UEDA HIROMI
IPC分类号： G06F13/00 , H04J3/00 , H04L1/22
摘要： PURPOSE:To prevent the missing of a reception cell even though a switching call lost in a communication system. CONSTITUTION:The system is provided with #0 and #1 system buffers 30 and 31 capable of transmission delay difference storage, xsi0 and #1 system switching cell detection sections 32 and 33, a selection section 34 selecting the output of the buffers 30 and 31 as the active system at its output, and an access/ switching control section 35 for buffers 30 and 31 based on signals from the sections 32 and 33. When the communication system buffer receiving the switching cells earlier is controlled to remain the reception cells and later and the other system receives switching cells before the amount reaches the threshold value, the switching of the communication system is performed by means of remaining reception cells of the standby buffer. When it exceeds the threshold value, the switching cell is judged to be missed and the missing of reception cells is prevented by using remaining reception cells if there is in the active system buffer without switching the system.

5. 发明专利

JP2002051035A BURST RECEPTION METHOD AND DEVICE 失效
公开(公告)号：JP2002051035A
公开(公告)日：2002-02-15
申请号：JP2000237534
申请日：2000-08-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO HIROYOSHI , KOYANAGI TOSHINORI , SUKEGAWA AYA , WATANABE JUNJI , SASAKI MASAHIRO
IPC分类号： H04J3/06 , H04L7/10 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide a burst receiving device consisting of a burst reception section and of a burst reception/synchronization circuit that can secure a normal retiming operation of the burst reception/synchronization circuit even when the burst reception section generates a noise inevitably by its characteristics. SOLUTION: The burst receiving device 1 consisting of the burst reception section 10 and of the burst reception/synchronization circuit 20 is provided with a reception identification signal generating means 31 that outputs a reception identification signal RD denoting that a level of a burst reception data Din received by the burst reception section 10 exceeds a predetermined level and with a mask means 32 that inhibits output burst reception data Bout from the burst reception section 10 to be given to the burst reception/synchronization circuit 20 until at least the reception identification signal generating means 31 outputs the reception identification signal RD.

6. 发明专利

JPH1098473A METHOD AND DEVICE FOR CONTROLLING TRAFFIC 失效
公开(公告)号：JPH1098473A
公开(公告)日：1998-04-14
申请号：JP25025196
申请日：1996-09-20
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IDE SHOTARO , NISHIKAWA KOJI , OTA SHINJI , KOYANAGI TOSHINORI , YAMASHITA TAKASHI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To reduce required memory capacity by expressing a minimum cell interval among traffic monitor parameters and a minimum cell interval among parameters to be used for finding the output time of cells through a traffic shaper in one common parameter. SOLUTION: A minimum cell interval T and a minimum cell interval T to be used for the shaper are expressed in the common parameter and after a violation is discriminated, CDV are immediately reduced. When real arrival time Ta of a cell is later than time based on theoretical rules, this cell is judged as a suitable cell and after TAT is changed to current time, the TAT is updated. When this arrival time is ealier, the difference between the theoretical cell arrival time TAT and the cell arrival time ta is compared with the level relation of a CDV allowable value 7τu and it is discriminated whether this cell is suitable or not. When the TAT-ta is larger than the τu, this cell is abandoned as a non-suitable cell but when the TAT-ta is smaller than the τu, shaping is performed as the suitable cell within an allowable range. Thus, the number of parameters to be stored can be reduced by two.

7. 发明专利

JPH06120972A SYNCHRONIZATION CONTROL SYSTEM 失效
公开(公告)号：JPH06120972A
公开(公告)日：1994-04-28
申请号：JP26614692
申请日：1992-10-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYANAGI TOSHINORI , OTA SHINJI , GOUNAI NOBUYUKI , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To perform switching without a hit by providing synchronizing cell detection parts in respective systems, stopping the read of the buffer of the system which detected a synchronizing cell when the synchronizing cell is detected in one of the systems and defining synchronization establishment at the point of time when the synchronizing cell of the succeeding system is detected. CONSTITUTION:In the case of assuming that the synchronizing cell of a first system arrives earlier for some reasons, a synchronization control part 3 freely reads from the buffer 1 until the synchronizing cell arrives. Whether the synchronizing cell arrives and is detected by the synchronizing cell detection part 5 or not is monitored and when the synchronizing cell is detected, cell reading from the buffer 1 of the first system is stopped and the arrival of the synchronizing cell of a second system is waited for. Thereafter, the control part 3 which recognized that the synchronizing cell of the second system is detected at the synchronizing cell detection part 6 defines that the synchronization is established and the selection of a selector 4 is made possible from that time as shown in a figure. Once after the synchronization is established, the selector 4 is controlled and the switching without the hit is possible in the case of switching between the first and second systems.

8. 发明专利

JP2002217979A CLAD TEST SYSTEM 失效
公开(公告)号：JP2002217979A
公开(公告)日：2002-08-02
申请号：JP2001015453
申请日：2001-01-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NTT COMM KK
发明人： KOYANAGI TOSHINORI , IDE SHOTARO , SUKEGAWA AYA , WATANABE JUNJI , AOKI HIROATSU , UCHIDA KAZUHIRO , RYU KAZUYA , YOSHIDA YUKIHIRO , KAMATA KATSUJI
IPC分类号： H04L12/70 , H04L12/66 , H04L29/14 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a reliable network having no non-test section, where related to a CLAD test system, a test function interlocked with a CLAD part is realized, which is combined with conventional STM and ATM transfer methods, in a device and network having an STM-ATM conversion function. SOLUTION: In a system, where an ATM device 1 is connected to an STM device 2 via an STM-ATM conversion device 3 for transferring information, at least a test means 30 for testing inside a CLAD part 20 is provided in the STM-ATM conversion device 3.

9. 发明专利

JPH10164062A FAULT MONITORING METHOD FOR ARITHMETIC CIRCUIT 失效
公开(公告)号：JPH10164062A
公开(公告)日：1998-06-19
申请号：JP31916496
申请日：1996-11-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IDE SHOTARO , KOYANAGI TOSHINORI , NISHIKAWA KOJI , IWASE RYOICHI
IPC分类号： G06F11/00 , H04L12/24 , H04L12/26 , H04L12/70 , H04L12/813 , H04L12/815 , H04L12/863 , H04M3/28 , H04M3/36 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To easily use a method in common to polishing and shaping without depending on algorithm with a small hardware scale by using an OH generation cell which is periodically generated at the time of converting an ATM cell format into a format in a device from the format of a transmission line. SOLUTION: Parameters for monitoring OH(overhead) generation cell are previously set for respective memories 42-45 and 401. A header detection part 40 identifies the cells. In the case of the OH generation cell, an OH generation cell period monitoring part 400 monitors an arriving period. When it is a regulated period, the parameters for OH generation cell are sequentially read from the respective memories 42-45 and 401 and the fault is monitored. When a polishing operation is executed and the cell is judged to be illegal in a conformity test and when a cell interval after shaping is not similar to that of the cell, it is judged that abnormality occurs in the arithmetic circuit. Thus, the increase of a circuit scale is small and miniaturization can be executed.

10. 发明专利

JPH06232892A SYNCHRONIZING CONTROL SYSTEM 失效
公开(公告)号：JPH06232892A
公开(公告)日：1994-08-19
申请号：JP1307193
申请日：1993-01-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYANAGI TOSHINORI , OTA SHINJI , SAKURAI HIROYA , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To establish synchronism in a short time without generating phase difference absorbing fluctuation and to control the synchronism so as to main tain it even when a cell is abandoned or any excess cell is inserted later concern ing the synchronizing control system for switching the cells of duplexed systems with no hit. CONSTITUTION:A synchronizing control part 3 continuously reads the same user cell from a buffer 2 of the auxiliary system (hunting) and when the user cell freely read from a buffer 1 of the present system is compared with it by a cell coincidence comparator circuit 5 and coincidence is detected, the synchronism is established. When the coincidence is not detected, however, hunting and free reading is performed until the coincidence is detected. When one buffer is made empty after this synchronism establishment, the reading of the other buffer is stopped and the synchronism is maintained by waiting the other system until the user cell arrives at one system.

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