专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH04281642A CROSS POINT TYPE SWITCH EMPLOYING COMMON BUFFER 失效
公开(公告)号：JPH04281642A
公开(公告)日：1992-10-07
申请号：JP4503891
申请日：1991-03-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OTA SHINJI , SHINOMIYA TOMOHIRO , TAKEO HIROSHI , FUKUDA SETSU , IGUCHI KAZUO
IPC分类号： H04Q3/52 , H04L12/931
摘要： PURPOSE:To allow the system to be compatible with the common buffer system and the cross point system by providing a memory and a function to select a data from the memory or an extended input port to a basic element. CONSTITUTION:A basic element 20-i is provided with a memory storing a data from an input port 1 and a function supplying the data extracted from the memory or a data from an extended input port 9 to an output port 2, and also with a function discriminating whether or not the data from the input port 1 is to be stored in its own memory and a function transferring the data from the input port 1 to the extended output port 10. Then basic elements 20-i are arranged in a matrix to process data corresponding to N sets of input output ports as a whole. Thus, the system has configuration coping with the common buffer system and also is compatible with the flexibility with respect to the expansion of the cross point configuration.

2. 发明专利

JPS60187137A CONTROL SYSTEM OF EQUALIZER 失效
公开(公告)号：JPS60187137A
公开(公告)日：1985-09-24
申请号：JP4363984
申请日：1984-03-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAJIYOU TAKAFUMI , TSUDA TOSHITAKA , FUKUDA SETSU , YOSHIDA KOUICHI
IPC分类号： H04B3/04 , H04B3/06 , H04B3/20
摘要： PURPOSE:To prevent the operation of a BT equalizer from being affected due to disturbance in an f equalizer output waveform at the transient state by starting equalization of a BT (bridged tape) equalizer after the transient response of the f (transmission frequency) equalizer is converged. CONSTITUTION:An automatic gain control circuit 2 is activated by a call signal, the control allows the f equalizer 3 to start equalization and an f equalized output signal A is settled after a time. Further, a delay circuit 4 retards a control signal 3 by a time tau sufficient for the equalizer 3 to complete equalization. The control signal C reaches logical 1 after the time tau, then the BT equalizer 5 starts the equalization to equalize the waveform where only the echo by the BT appears. Thus, the operation of the BT equalizer is not affected because of the disturbance of the f equalizer output waveform at the transient state.

3. 发明专利

JPS60186132A DIGITAL CONTROL TYPE ADAPTIVE AGC SYSTEM 失效
公开(公告)号：JPS60186132A
公开(公告)日：1985-09-21
申请号：JP4271284
申请日：1984-03-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAJIYOU TAKAFUMI , TSUDA TOSHITAKA , YAMAGUCHI KAZUO , FUKUDA SETSU , TAKADA AKIHIKO , KIMURA TADAKATSU , ISHIKAWA MASAYUKI
IPC分类号： H04B3/06 , H03G3/20 , H04B3/04
摘要： PURPOSE:To reduce the scale of hardware by detecting a pattern of N successive levels 0 before a level 1 in a reception equalized signal, and using only the peak value contained it as gain updating information on a line equalizer. CONSTITUTION:An input signal is inputted to a line equalizer 1 with discrete equalization characteristics in the AGC equalizer of a PCM transmission device. The output signal of the equalizer is passed through a peak detecting circuit 3, initial leading-in circuit 4, selector 6, and up/down counter 7 at the start of communication to control the gain of the equalizer and then a clock CLK1 put in phase with the reception equalized signal by a timing extracting circuit 2 is outputted to an adaptive AGC circuit 5. The circuit 5 detects the pattern of N successive levels 0 before the level 1 from the circuit 3 to extract only its peak value, and updates the gain of the equalizer 1 through the selector 6 and counter 7. Consequently, the number of steps of the counter is decreased to reduce the scale of the integrating circuit of the circuit 5.

4. 发明专利

JPS607240A TIMING EXTRACTING CIRCUIT 失效
公开(公告)号：JPS607240A
公开(公告)日：1985-01-16
申请号：JP11395183
申请日：1983-06-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAJIYOU TAKAFUMI , TSUDA TOSHITAKA , YAMAGUCHI KAZUO , FUKUDA SETSU , ISHIKAWA MASAYUKI , TAMAKI NORIO
IPC分类号： H04L25/52 , H03G11/00 , H04L7/027 , H04L25/06 , H04L7/02
摘要： PURPOSE:To prevent the fluctuation of a slice level from being caused even if the characteristic of an active element is varied by supervising the output of an equalizing amplifier, and slicing the output by applying the linear amplification when the output is at the reference slice level or over, and holding the value equal to the slice level when the output is at the reference slice level or below. CONSTITUTION:A nonlinear amplifier 14 consists of a linear amplifier (amplifier and switch circuit) 24 and a comparator 26. The amplifier 24 amplifies linearly an input signal when an input signal S3 is higher than the slice level, and has a characteristic holding an amplifier output voltage at a level equal to the slice level when the input signal is lower, and the comparator 26 receives the input signal S3 and a voltage VB for deciding slice level from a reference voltage source 20 and executes the changeover control for the amplifier 24. Differential pair transistors (TRs) 32, 34 flow an equal current when S3=SB. The comparator 26 changes over a switch 42 in the position of the contact (b) when S3 VB and an output at S3=VB is held when S3

5. 发明专利

JPS605633A BRIDGED TAP EQUALIZER 失效
公开(公告)号：JPS605633A
公开(公告)日：1985-01-12
申请号：JP11334083
申请日：1983-06-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUDA TOSHITAKA , YAMAGUCHI KAZUO , NAKAJIYOU TAKAFUMI , FUKUDA SETSU , ISHIKAWA MASAYUKI , TAMAKI NORIO
IPC分类号： H03H15/00 , H04B3/04 , H04B3/06 , H04L25/03
摘要： PURPOSE:To equalize at high stability in relatively short time by detecting arrival of a pulse signal at equalizer input and controlling an inhibition gate by output that delayed the detection pulse one step. CONSTITUTION:An equalizer output signal is delayed by plural steps of delay cicrcuits D1-D3 through an inhibition gate IHG. Delayed output of each step is multiplied by coefficients C1-C3 by multipliers M1-M3 respectively, and output of multipliers M1-M3 is subtracted from an input signal IN by an arithmetic circuit SM to obtain output of a bridged tap equalizer. When the input signal of the equalizer is pulselike form, this is delayed by the time 1T for a time slot by the circuit D1, and this is detected by a pulse detecting circuit PD. The detected pulse is waveform shaped by a time constant circuit TC, and a gate IHG is controlled by the signal, and the pulse to be inputted next is inhibited by IHG. Accordingly, no signal due to secondary echo occurs, and action is controlled at high speed.

6. 发明专利

JP2000299747A NETWORK TERMINATOR 失效
公开(公告)号：JP2000299747A
公开(公告)日：2000-10-24
申请号：JP10712099
申请日：1999-04-14
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , FUJITSU LTD , HITACHI LTD
发明人： FUJIKAWA SHUICHI , YAMANO SEIICHI , KOMATSU KAZUTOSHI , SAKAI KAZUNORI , FUKUDA SETSU , TAJIMI NOBURO
IPC分类号： H04M11/00 , H04L12/02
摘要： PROBLEM TO BE SOLVED: To obtain a network terminator that can suppress power consumption at communication and also reduce power of a digital service unit. SOLUTION: The network terminator 1 that is connected to a digital service unit 10 and has a polarity inversion detection circuit 5, a dial circuit 2, and a layer 1 control section 7 and a layer 2 control section 8 respectively controlling the polarity inversion detection circuit 5 and the dial circuit 2, is provided with a positive polarity current detection circuit 3 that detects a DC current with positive polarity flowing through a subscriber line, a DC termination resistor that supplies a current with opposite polarity, a changeover circuit 6 that connects or disconnects the DC termination resistor, and a polarity change decision section 4 that controls the changeover circuit 6 on the basis of the detection result of the positive polarity current detection circuit 3. The polarity change decision section 4 allows the changeover circuit 6 to connect or disconnect the DC termination resistor on the basis of the decision result.

7. 发明专利

JPS6441343A TIMING RECOVERY CIRCUIT 失效
公开(公告)号：JPS6441343A
公开(公告)日：1989-02-13
申请号：JP19634387
申请日：1987-08-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMATO SEIICHI , FUKUDA SETSU , KUMOSAKI KIYOMI
IPC分类号： H04L7/00 , H04L7/02 , H04L7/027 , H04L12/28 , H04L25/40
摘要： PURPOSE:To accurately detect an error of a frequency through the decision of the convergence of a frequency error detection period by applying sufficient initial pull-in at first, confirming the convergence, applying initial setting of frequency error detection by the convergence decision at the self-traveling start point of time afterward, setting a detection criterion so as to apply convergence decision corresponding to the sequence. CONSTITUTION:An initial convergence deciding means 44 applies correction so as to match the phase of a recovered clock RC with that of a reception signal by the pull-in of the reception signal and decides it to be the initial convergence depending on the repetition of the consecutive phase inversion of the phase comparison result A. A self-traveling deciding means 45 decides it as the start of self-traveling by the initial phase inversion of the phase comparison result by using a reception signal at an optional point of time of self-traveling start decision after the initial convergence. Then a convergence deciding means 46 applies the convergence decision when the phase comparison result A represents the phase inversion by the repulling-in of the reception signal after the self-traveling of prescribed time. Thus, the convergence decision according to the sequence is applied and accurate frequency error detection is attained by the convergence decision for the frequency error detection period.

8. 发明专利

JPS60187151A DIGITAL BURST TRANSMITTING CIRCUIT 失效
公开(公告)号：JPS60187151A
公开(公告)日：1985-09-24
申请号：JP4363884
申请日：1984-03-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUDA TOSHITAKA , MURANO KAZUO , NAKAJIYOU TAKAFUMI , FUKUDA SETSU , WATAYA HIDEO , YOSHIDA KOUICHI
IPC分类号： H04L5/16 , H04L5/14
摘要： PURPOSE:To simplify a subscriber-side circuit by providing an echo compensating circuit for transmission and reception at a station side in a digital burst transmission system which uses one transmission line on time-division basis for two-way transmission between a subscriber and the station. CONSTITUTION:A burst signal is transmitted from the subscriber to the station through a transmitting circuit 2, transmission line 1, f (frequency) AGC circuit 7, echo compensating circuit 8, and receiving circuit 9, and a burst signal is transmitted from the station to the subscriber through an echo compensating circuit 11, transmitting circuit 6, transmission line 1, f AGC circuit 3, and receiving circuit 5. The transmission-side echo compensating circuit 11 and reception- side circuit 8 of the station 1 have the same frequency characteristics. One echo compensating circuit 12 is used for both transmission and reception in common.

9. 发明专利

JPS59221127A TIME CONSTANT CIRCUIT 失效
公开(公告)号：JPS59221127A
公开(公告)日：1984-12-12
申请号：JP9658383
申请日：1983-05-31
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKUDA SETSU , TSUDA TOSHITAKA , YAMAGUCHI KAZUO , NAKAJIYOU TAKAFUMI , KIMURA TADAKATSU , TAMAKI NORIO
IPC分类号： H03H21/00 , H04B3/04 , H04B3/06 , H04L25/03
摘要： PURPOSE:To apply coefficient correction only to a stationary equalizing error by utilizing a difference between a tap coefficient correcting signal at steady-state and a correcting signal produced suddenly in a tap coefficient control circuit of an automatic equalizer. CONSTITUTION:An FF2, an FF3 and an EOR gate C constitute a circuit discriminating whether the tap coefficient correcting signal is of the same polarity or opposite polarity, and if the signal is inputted continuously, an output of the EOR gate C is at ''0'' and when the polarity is opposite, the output is at ''1''. When the output is at ''1'', a continuous number counter H is reset by an FF4 and a gate G and also an NAND gate D and an AND gate A revise the coefficient of an equalizer (not shown). When an output of the EOR gate C is at ''0'', the continuous number cunter H counts the continuous number by the Q' output of the FF4 and when the count value reaches a prescribed number, the coefficient of the equalizer is revised by the output of the AND gate F and the Q output of the FF1 resets the counter H.

10. 发明专利

JPH06284387A VIDEO SIGNAL INFORMATION TRANSMISSION SYSTEM 失效
公开(公告)号：JPH06284387A
公开(公告)日：1994-10-07
申请号：JP6643593
申请日：1993-03-25
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKUDA SETSU , NISHIOKA YOSHIHIRO , NISHIZAWA YOSHIJI , MIWA TAKUYA
IPC分类号： H04N7/00 , H04N7/22 , H04N21/647
摘要： PURPOSE:To effectively utilize the idle transmission data of a synchronizing signal part in an encoded video signal, regarding a system transmitting video signal information. CONSTITUTION:In a video signal transmitter where an A/D conversion means 1 converting video signals including synchronizing signals into digital data, and a synchronizing detection means 2 generating a synchronizing flag for a synchronizing signal period are provided, a transmitter multiplexing video data and a synchronized flag and transmitting it, a D/A conversion means 3 converting reception video data into an analog signal and a synchronizing generation means 4 generating an analog synchronizing signal for a sychronizing flag reception period are provided, and a receiver adding the synchronizing signal to the video signal and reproducing an original signal is provided, information data is converted into the same speed as a video, the data is multiplexed to the video for a synchronizing signal period and transmitted by providing a speed conversion means 5 on the transmitter, and the information data separated for the synchronizing flag reception period is converted into original speed and original data is reproduced by providing a speed conversion means 6 on the receiver.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式