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1. 发明专利

JPH0628296A METHOD AND DEVICE FOR SELECTING AND OUTPUTTING INFORMATION 失效
公开(公告)号：JPH0628296A
公开(公告)日：1994-02-04
申请号：JP20453092
申请日：1992-07-08
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , KIMURA SHUJI , YAMADA SHIGEKI , SASAKI YASUHIKO , MARUYAMA AKIRA
IPC分类号： G06F13/14
摘要： PURPOSE:To easily output holding information in the device by setting what kind of information to be transmitted and to which output port the information is to be transmitted without burdening a large load on software. CONSTITUTION:Plural output ports 31 latching the selected transmission information, rewritable transmission information holding memory 32 holding plural transmission information, and rewritable connection information holding memory 33 holding the address of the memory 32 storing the transmission information sent to the output port as connection information and applying the connection information as the read address to the memory 32, address generation circuit 34 successively generating the address corresponding circuit 34 successively generating the address to the section 33, and control circuit 35 accepting the address of the circuit 34 and writing the transmission information read out from the memory 32 to the output port 31 corresponding to the address are provided.

2. 发明专利

JPH05199240A BUS MONITOR SYSTEM 失效
公开(公告)号：JPH05199240A
公开(公告)日：1993-08-06
申请号：JP731792
申请日：1992-01-20
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SUZUKI SHOJI , YAMADA SHIGEKI
IPC分类号： H04L29/14 , H04L12/24 , H04L12/26 , H04L12/40
摘要： PURPOSE:To surely monitor the bus of a line with simple configuration. CONSTITUTION:This system is provided with a monitor bit insertion part 1 to insert bit information PB for bus monitor at the prescribed one empty bit position of a transmitting frame and a monitor bit extraction inspection part 2 to execute inspection by extracting the bit information PB for bus monitor from the one empty bit position of the received frame, and the bus of the line is inspected by alternating the bit information PB for bus monitor between '0' and '1' in the unit of a frame. Preferably, the alternating phase of bit information CB for bus inspection 15 matched to the alternating phase of the bit information PB for bus monitor by detecting the change of the bit information PB for bus monitor from '0' to '1' or from '1' to '0' extracted by the monitor bit extraction inspection part 2.

3. 发明专利

JPH04114248A MEMORY DEVICE 失效
公开(公告)号：JPH04114248A
公开(公告)日：1992-04-15
申请号：JP23429190
申请日：1990-09-04
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , NAKAYAMA SHUNICHI , YAMADA SHIGEKI
IPC分类号： G06F12/16
摘要： PURPOSE:To efficiently use a memory space without necessity for newly executing the preparation / transfer processing of a backup data by providing a backup memory and a means to select a main memory in the case of normal read and to select the backup memory in the case of alarm read. CONSTITUTION:This device is equipped with a backup memory 1C, which is accessed by a CPU 2 with the same write / read address as a backup area 1BB on a main memory 1B, and a means 3 to select the main memory 1B in the case of a normal operation and to select the backup memory 1C in the case of an alarm operation. In this case, since the selecting means 3 is switched from the main memory 1B to the selection of the backup memory 1C in the case of recovery rise after interrupting power supply or the like, the backup memory 1C can be accessed and the backup data can be read. Thus, it is not necessary to newly prepare and transfer the backup data to be stored in the backup memory 1C, and the software load of the CPU is reduced.

4. 发明专利

JPS5699559A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5699559A
公开(公告)日：1981-08-10
申请号：JP86380
申请日：1980-01-10
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NAKAMURA YUKIO , YAMADA SHIGEKI , YAMAUCHI HIDEO , INUI YOSHIO , FUJITA HIROSHI , KIMURA AKIO
IPC分类号： G06F15/16 , G06F12/00 , G06F13/16 , G06F15/177
摘要： PURPOSE:To realize an economical load distribution type multiprocessor system, by making it possible that respective control devices use the program memory provided commonly in time division. CONSTITUTION:Control processing device 11 executes one instruction during the time from the start of the control clock period to, for example, the 3/4 period and outputs the memory address of program memory 200 to address line 31 during the rest 1/4 period. Selector circuit 300 selects address line 31 during the said 1/4 period and inputs address information to memory 200. The instruction output to output line 401 of memory 200 is distributed to device 11 by distributing circuit 400. Device 11 sets this instruction in itself and executes it at the next period. Other control devices 12-14 are operated similarly by control clocks PC2-PC4 whose phase is shifted successively from the phase of control clock PC1 of device 11 by every 1/4 period. As a result, memory 200 is used time-divisionally.

5. 发明专利

JPS5432042A ORIGINAL SETTING SYSTEM FOR MICROPROGRAM ADDRESS 失效
公开(公告)号：JPS5432042A
公开(公告)日：1979-03-09
申请号：JP9801577
申请日：1977-08-15
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： OOKAWA KAZUMASA , YAMADA SHIGEKI , YASUI YUTAKA
IPC分类号： G06F9/26 , G06F9/22
摘要： PURPOSE:To ensure generation of multi-type patterns from just one type of the specific fixed address pattern, by modifying the fixed address according to the inside state against the fixed address which is shown by the microprogram.

6. 发明专利

JPH06309275A PREFERENCE SELECTING CIRCUIT 失效
公开(公告)号：JPH06309275A
公开(公告)日：1994-11-04
申请号：JP9322393
申请日：1993-04-20
申请人： FUJITSU LTD
发明人： YAMADA SHIGEKI , OKU TATSUYA , MARUYAMA AKIRA
IPC分类号： G06F13/362
摘要： PURPOSE:To improve the processing speed and to reduce the scale of a preference selecting circuit which selects a single input signal for each of plural slave stations in the multiple processing based on a prescribed preferential condition. CONSTITUTION:An existing choice preferential gate means 1 generates the control data A1-An which invalidated the input signals of younger numbers than a selected one based on the state data D1-Dn which show the valid input signals of a frame and the pre-selection control data B1'-Bn' which show the selected input signals respectively. Then a delay means 2 is added to delay the control data of the means 1 by one bit, together with a gounger number order selection gate means 3 which receives input of the control data delayed by the means 2 and validates only the input signal of the youngest number among those input signals which are valid in the control data, and a dual port RAM means 4 which stores the selection control data B1-Bn and then outputs these data as the data B1'-Bn' in the corresponding time slot of the next frame.

7. 发明专利

JPH05199678A POWER SUPPLYING SYSTEM FOR PACKAGE 失效
公开(公告)号：JPH05199678A
公开(公告)日：1993-08-06
申请号：JP710192
申请日：1992-01-20
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , WATANABE NAOKI , NARA KOICHI , YAMADA SHIGEKI , HANIYUDA KEN , KATO TAKEO
IPC分类号： H02J1/00 , H02J9/00 , H02J9/06 , H05K7/14
摘要： PURPOSE:To provide a power supplying system for package which can minimize its power supply trouble when a power source module becomes faulty for communication equipment, etc., in which power is supplied to load circuits in a plurality of packages constituting a unit from power source modules respectively incorporated in the packages. CONSTITUTION:A power source module 11, power source fault detecting means 12 which detects the abnormal output voltage of the module 11, switching control means 13 which sends a switching control signal in accordance with information from the means 12, and switching means 14 which operates under the control of the control means 13 are incorporated in each package 10 and, when the module 11 becomes faulty, the detecting means 12 detects the abnormal output voltage of the module 11 and the switching means 14 operates under the control of the control means 13 which receives the fault information. As a result, electric power is supplied to a load from an emergency power source.

8. 发明专利

JPH03261300A CPU RESET SYSTEM FOR REMOTE EQUIPMENT 失效
公开(公告)号：JPH03261300A
公开(公告)日：1991-11-21
申请号：JP5948390
申请日：1990-03-09
申请人： FUJITSU LTD
发明人： NARA KOICHI , SUZUKI SHOJI , YAMADA SHIGEKI
IPC分类号： H04B17/00 , H04B17/18 , H04B17/29 , H04Q9/00
摘要： PURPOSE:To reset a CPU of an opposite equipment with remote control from its own station by providing a reset pattern detection circuit detecting a bit pattern of a reset command from its own station without CPU processing and a gate opened at a CPU fault of the opposite station to an opposite station equipment. CONSTITUTION:A CPU fault of an opposite station B is detected by its own station A as disabled communication. A cause to disabled communication is not only a CPU fault but the fact of CPU fault is checked and a reset command with a specific bit pattern is sent to the opposite station B through a control path CP1 from its own station A. When a CPU is faulty, a CPU fault monitor circuit 12 of the opposite station equipment gives an output to open the gate G, and when the reset command sent from its own station A is detected by a reset pattern detection circuit 10 of the opposite station B, the output of the circuit 10 passes through the gate G and enters a reset terminal RST of the CPU to reset the CPU. Thus, the processor CPU of an unattended opposite station equipment is reset by an attended own station A by remote control.

9. 发明专利

JPS5843043A CALL INSTRUCTION SYSTEM FOR DATA PROCESSOR 失效
公开(公告)号：JPS5843043A
公开(公告)日：1983-03-12
申请号：JP14134181
申请日：1981-09-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MATSUSHITA MASAYOSHI , YAMADA SHIGEKI , SATOU NORIO , FUJISAWA MITSURU , IKUTA AKIRA , OCHIAI SHIGEO
IPC分类号： G06F9/42
摘要： PURPOSE:To realize easily a reentrant subroutine, by performing automatically the evacuation of the register group, the security of a working area and the setting of a static link respectively on a stack and by means of hardwares when the subroutine is called. CONSTITUTION:The contents of a general-purpose register 3 is evacuated to a work register 5. The register 3 is shown by a static link address designating register number of an instruction which is read out by a main storage device 1. Then a program status word 4 is pushed down to a stack, and the contents of the head address of a subroutine is evacuated to a work register 6. The contents of the register 3 is pushed down to a stack in accordance with a register save pattern. The contents of a work register 9 is subtracted by an operator 10, and the contents of the register 6 and the static link address of the register 5 are pushed down to the stack. Finally the contents of the word 4 receives the addition of (1) through the operator 10, and the head address of the main body of the subroutine program is obtained for execution.

10. 发明专利

JPS57106960A DATA PROCESSOR WITH INTERRUPTION CONTROL FACILITY 失效
公开(公告)号：JPS57106960A
公开(公告)日：1982-07-03
申请号：JP18257380
申请日：1980-12-23
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： YAMADA SHIGEKI , MATSUSHITA MASAYOSHI , FUJISAWA MITSURU , MASUDA TAKESHI , UKAWA YOSHIHIRO
IPC分类号： G06F9/46 , G06F9/42 , G06F9/48
摘要： PURPOSE:To improve the efficiency of interruption, to speed processing, and to make the interruption flexible, by automatically securing a work area, used by the stand-by and interruption processing program of a register during interruption, through hardware. CONSTITUTION:In an interruption processing program, the 1st control information field WAS for specifying a register RSA to be enqueued in a stack and the 2nd control information field RSP for specifying the size of a work area WA used by the interruption processing program are provided. Once interruption is caused, the contents of the register are enqueued in the register stand-by area RSA in the stack in accordance with the 1st control information field WAS, and the work area WA is secured in the stack in accordance with the 2nd control information field RSP.

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