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1. 发明专利

JPH09128271A GATHERING SYSTEM FOR MONITOR DATA AND ITS MONITORED UNIT 失效
公开(公告)号：JPH09128271A
公开(公告)日：1997-05-16
申请号：JP28866995
申请日：1995-11-07
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , WATANABE TOSHIAKI , TSUJI HIDEO
IPC分类号： G06F11/34 , G06F17/40 , H04B17/00
摘要： PROBLEM TO BE SOLVED: To easily analyze a monitored object in detail in any case. SOLUTION: Respective monitored units 11 -1n have data for system monitoring obtained by integrating detailed data on the monitored objects and the contents of the detailed data, and a monitor unit 2 ORs current detailed data gathered from the monitored units and past detailed data (accumulated data) read out of a memory 27, and stores the results in a different memory 27 from the data for system monitoring. Further, the monitored units 11 -1n when generating the data for system monitoring by integrating the detailed data on the monitored objects OR the current detailed data and past detailed data read out of the memory 17 and stores the results in the memory 17, and the monitor unit 2 monitors the operation state of the system according to the data for system monitoring gathered from the monitored units.

2. 发明专利

JPH0795166A TEST EQUIPMENT FOR TRANSMISSION SYSTEM 失效
公开(公告)号：JPH0795166A
公开(公告)日：1995-04-07
申请号：JP23363393
申请日：1993-09-20
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , YOSHIDA KATSUMI
IPC分类号： H04M3/26 , G01R31/28 , H04B17/00
摘要： PURPOSE:To prevent an alarm from being outputted continuously due to a pseudo synchronization state caused in the test equipment. CONSTITUTION:The test equipment 10 having a test pattern insert section 11 inputting a test pattern P to a transmission system TS being a test object and a test pattern confirmation section 12 checking a signal passing through the transmission system TS and discriminating whether or not the test pattern P is normally received is provided with a non-test pattern additional transmission section 20 sending a non-test pattern not identical to the test pattern P for a predetermined time (t) in succession to the end of the test.

3. 发明专利

JPH0679358B2 失效
公开(公告)号：JPH0679358B2
公开(公告)日：1994-10-05
申请号：JP3219286
申请日：1986-02-17
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , MUNAKATA KOJI
IPC分类号： G07G1/12 , G07G1/00 , G07G1/14

4. 发明专利

JPH0628296A METHOD AND DEVICE FOR SELECTING AND OUTPUTTING INFORMATION 失效
公开(公告)号：JPH0628296A
公开(公告)日：1994-02-04
申请号：JP20453092
申请日：1992-07-08
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , KIMURA SHUJI , YAMADA SHIGEKI , SASAKI YASUHIKO , MARUYAMA AKIRA
IPC分类号： G06F13/14
摘要： PURPOSE:To easily output holding information in the device by setting what kind of information to be transmitted and to which output port the information is to be transmitted without burdening a large load on software. CONSTITUTION:Plural output ports 31 latching the selected transmission information, rewritable transmission information holding memory 32 holding plural transmission information, and rewritable connection information holding memory 33 holding the address of the memory 32 storing the transmission information sent to the output port as connection information and applying the connection information as the read address to the memory 32, address generation circuit 34 successively generating the address corresponding circuit 34 successively generating the address to the section 33, and control circuit 35 accepting the address of the circuit 34 and writing the transmission information read out from the memory 32 to the output port 31 corresponding to the address are provided.

5. 发明专利

JPH05199240A BUS MONITOR SYSTEM 失效
公开(公告)号：JPH05199240A
公开(公告)日：1993-08-06
申请号：JP731792
申请日：1992-01-20
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SUZUKI SHOJI , YAMADA SHIGEKI
IPC分类号： H04L29/14 , H04L12/24 , H04L12/26 , H04L12/40
摘要： PURPOSE:To surely monitor the bus of a line with simple configuration. CONSTITUTION:This system is provided with a monitor bit insertion part 1 to insert bit information PB for bus monitor at the prescribed one empty bit position of a transmitting frame and a monitor bit extraction inspection part 2 to execute inspection by extracting the bit information PB for bus monitor from the one empty bit position of the received frame, and the bus of the line is inspected by alternating the bit information PB for bus monitor between '0' and '1' in the unit of a frame. Preferably, the alternating phase of bit information CB for bus inspection 15 matched to the alternating phase of the bit information PB for bus monitor by detecting the change of the bit information PB for bus monitor from '0' to '1' or from '1' to '0' extracted by the monitor bit extraction inspection part 2.

6. 发明专利

JPH04257136A SYSTEM AND METHOD FOR MONITORING SELECTING DEVICE 失效
公开(公告)号：JPH04257136A
公开(公告)日：1992-09-11
申请号：JP3917791
申请日：1991-02-08
申请人： FUJITSU LTD
发明人： SHIRAI HIROAKI , MARUYAMA AKIRA , KIMURA SHUJI
IPC分类号： H04L1/22 , H04M3/22
摘要： PURPOSE:To preliminarily detect and prevent the fault caused at the time of switching by checking a selecting circuit for not only a selected circuit system but also non-selected circuit systems with respect to the system and the method of a selecting device provided with plural circuit systems and the selecting circuit which selects one or more of circuit systems and allows signals from selected circuit systems to pass through. CONSTITUTION:A selecting circuit 30 selects output signals of one or more of plural circuit systems 10 and allows selected signals to pass through from the output side. In accordance with indication or the like, the selecting circuit 30 is switched to select another circuit system. When the selected circuit system is made unoperated, the selecting circuit 30 successively selects circuit systems. After selection, a check pattern sending part 201 provided correspondingly to the selected circuit system sends a check pattern, which discriminates this circuit system, to the selecting circuit 30. Then, each check part 50k provided on the output side of the selecting circuit 30 checks whether the same pattern as the check pattern sent from the check pattern sending part 20i is outputted through the selecting circuit 30 or not.

7. 发明专利

JPH02148939A DATA TRANSMISSION CONTROL SYSTEM 失效
公开(公告)号：JPH02148939A
公开(公告)日：1990-06-07
申请号：JP29956188
申请日：1988-11-29
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SHIRAI HIROAKI , NARA KOICHI
IPC分类号： H04L1/08 , H04L1/16 , H04L13/16 , H04L29/02
摘要： PURPOSE:To simply transmit an identification data by reading the identification data stored in a buffer memory repetitively, sending the result to an opposite equipment and sending a general data after the notice being the result of recognizing the identification data by an opposite equipment is received through the switching control. CONSTITUTION:A processor 1 applies control to store the identification data of its own equipment transferred from a host equipment to a buffer memory 2 and a transmission means 3 is started when the identification data is sent to the opposite equipment. The started transmission means 3 reads the identification data stored in the buffer memory 2 repetitively and sends the data to the opposite equipment asynchronously. When the recognition notice of the identification data from the opposite equipment is received, a switching means 4 applies the identification data and a general data by a control signal based on the notice of recognition. Thus, the identification data of its own equipment is sent asynchronously without increasing the processing load of the processor at the rise of system and at data transmission.

8. 发明专利

JPH0260248A CLOCK SELECTING CIRCUIT 失效
公开(公告)号：JPH0260248A
公开(公告)日：1990-02-28
申请号：JP21142588
申请日：1988-08-25
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , HASHIMOTO KENICHI , NARA KOICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To avoid data errors by frequency-dividing a free-running clock in a phase locked loop circuit when a clock sequence is switched, generating a frame clock, latching sequence selection order information, input clock interruption information and select information by means of the frame clock and generating select information. CONSTITUTION:When a clock sequence n1 comes to an interruption state, a PLO circuit 3 starts free running. The frequency divider 4 frequency-divides the free-running clock outputted from the PLO circuit 3 into the clock frequency 8KHz of a synchronous network, and gives it to FF5 as the frame clock. Consequently, select information given to a selector 2 from ROM11 through FF12 is synchronized with the free-running clock outputted from the PLO circuit 3. Thus, the PLO circuit 3 can absorb fluctuation even if the phase of a clock sequence n2 which the select information selects slightly fluctuates, and therefore the data errors are prevented from occurring.

9. 发明专利

JPH01236829A DUPLICATED INTERFACE SWITCHING SYSTEM 失效
公开(公告)号：JPH01236829A
公开(公告)日：1989-09-21
申请号：JP6426688
申请日：1988-03-17
申请人： FUJITSU LTD
发明人： NAKAYAMA SHUNICHI , KIMURA SHUJI , NARA KOICHI , SUZUKI SHOJI , MARUYAMA AKIRA
IPC分类号： H04B1/74 , H04B17/40
摘要： PURPOSE:To surely execute the switching by detecting an abnormality at both sides, executing the switching and surely executing the switching when only one side direction between the interfaces of both devices duplicated for the present use and the preliminary use is different. CONSTITUTION:A receiving switching control part 20 controls a present use interface 3-1 and a preliminary use interface 3-2, transmitting data with a control signal C as a code '0' are sent to an opponent device 1, a transmitting switching control part 10 of the device 1 detects that the control signal C in the receiving data is a code '0', and the transmitting data inputted to the device 1 are switched and transmitted from the present use side interface 3-1 to the preliminary use side interface 3-2. The device 2 receives the data with the preliminary use interface 3-2, the receiving switching control part 20 detects that the control signal C of the receiving data is a code '0', the receiving output edge switched to a preliminary side earlier is held as it is, and the receiving data received by the preliminary interface 3-2 are outputted to the external part. Thus, a correct switching is executed.

10. 发明专利

JPS63185243A AUTOMATIC LINE SETTING SYSTEM 失效
公开(公告)号：JPS63185243A
公开(公告)日：1988-07-30
申请号：JP1599187
申请日：1987-01-28
申请人： FUJITSU LTD
发明人： NAKAYAMA SHUNICHI , KIMURA SHUJI , NARA KOICHI , MARUYAMA AKIRA
IPC分类号： H04J3/00
摘要： PURPOSE:To automatically perform a line setting, by reading the classification data of a mounted CH board by a common control part. CONSTITUTION:The common control part 1 in a time divisional multiplexing device is provided with a processing part 2 which executes a processing according to a program, and is connected to housing parts(shelves) 3-1-3-m via a bus 6. In each of the housing parts 3-1-3-m, the mounted area of the CH board is connected to the bus 6 with backboard wiring, etc., and when the CH boards 4-1-4-n are mounted, they are connected with the backboard wiring and a connector. At the common control part 1, to which time slot and in which path the CH board should be allocated, or to which multiframe it should be allocated is processed based on the classification data of the mounted CH board according to a line setting program, thereby, automatic line setting can be performed.

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