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    • 5. 发明专利
    • System for generating interrupt address
    • 用于生成中断地址的系统
    • JPS57127252A
    • 1982-08-07
    • JP1203981
    • 1981-01-29
    • Fujitsu Ltd
    • UKAWA YOSHIHIROSAKAMOTO YASUHIKO
    • G06F13/24G06F9/48
    • G06F9/4812
    • PURPOSE:To generate a versatile interrupt destination address with a simple circuit, by gathering plural interruption sources to make them into binary data and providing a means which uses this binary data as an address to access a random access memory. CONSTITUTION:Plural interruption sources ISi (i=0-n) are gathered to make them into binary data IS0-ISn and are inputted as addresses of a ROM. When a signal which prescribes the timing of generation of an interrup address is given as a chip enable signal CG, output information A0-Am (binary) indicating the interrupt destination address are outputted after the access time designated for the ROM.
    • 目的:通过收集多个中断源使其成为二进制数据,并提供一种使用该二进制数据作为地址来访问随机存取存储器的手段,以简单的电路生成通用的中断目标地址。 构成:收集多个中断源ISi(i = 0-n)使其成为二进制数据IS0-ISn,并作为ROM的地址输入。 当指定了产生中断地址的定时的信号作为芯片使能信号CG时,指定中断目的地地址的输出信息A0-Am(二进制)在为ROM指定的访问时间之后被输出。