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1. 发明专利

JPH05197452A POWER SUPPLY SYSTEM 失效
公开(公告)号：JPH05197452A
公开(公告)日：1993-08-06
申请号：JP847492
申请日：1992-01-21
申请人： FUJITSU LTD
发明人： WATANABE NAOKI , MARUYAMA AKIRA
IPC分类号： G06F1/26 , G06F1/28
摘要： PURPOSE:To provide a power supply system in which it is possible to cope with the fault of an on-board power source without enlarging a package on which the on-board power source is mounted, in the power supply system when the fault of the power source occurs in a communication equipment or the like. CONSTITUTION:A common preliminary power source 20 is provided at the outside of each package 10 having an on-board power source 1. Then, each package is equipped with a power source fault detecting part 2 which detects the fault state of the on-board power source, and a power source switching part 3 which switches the on-board power source to the stand-by power source at the time of the occurrence of the fault of the on-board power source.

2. 发明专利

JPH0218776B2 失效
公开(公告)号：JPH0218776B2
公开(公告)日：1990-04-26
申请号：JP9350383
申请日：1983-05-27
申请人： FUJITSU LTD
发明人： IKUTA KOJI , AOKI KOJI , YAMADA HIROSHI , WATANABE NAOKI
IPC分类号： H04B1/76 , H04B3/10 , H04L25/03

3. 发明专利

JPS6351587B2 失效
公开(公告)号：JPS6351587B2
公开(公告)日：1988-10-14
申请号：JP13335681
申请日：1981-08-27
申请人： FUJITSU LTD
发明人： IKUTA KOJI , AOKI KOJI , YAMADA HIROSHI , WATANABE NAOKI
IPC分类号： H04L27/06 , H04B1/68 , H04L27/02 , H04L27/18 , H04L27/227

4. 发明专利

JPS63226155A MODEM EQUIPPED WITH SELF-DIAGNOSING FUNCTION 失效
公开(公告)号：JPS63226155A
公开(公告)日：1988-09-20
申请号：JP6042587
申请日：1987-03-16
申请人： FUJITSU LTD
发明人： YAMADA HIROSHI , WATANABE NAOKI
IPC分类号： H04L27/18
摘要： PURPOSE:To secure the data of an important line in one direction by disconnecting a transmission side and executing no loop-back diagnosis of transmission and reception, utilizing as it is the transmitting function of the transmission side, and bringing a reception side to a loop-back self-diagnosis, when a fault is generated in the reception side of a MODEM. CONSTITUTION:On the output sides of an encoder 1, a D/A converter 2 and the modulator 3 of a transmission side, branching circuits 9-11 are provided, respectively, and on the input sides of a demodulator 4, an equalizer 5, an A/D converter 6 and the decoder 7 of a reception side, switching circuits 12-15 are provided, respectively, and by connecting the branching circuits and the switching circuits, respectively, the loop-back of each stage is generated, and by a collating circuit 8 connected between the encoder 1 and the decoder 7, the fault state of each stage is diagnosed. In such a way, even if a fault is generated in the reception side of the MODEM, the loop-back test in its own station can be executed and the fault of the reception side can be diagnosed, in a state that a data transmission of the transmission side remains continued.

5. 发明专利

JPS60253331A INITIAL VALUE SETTING SYSTEM IN CONTROL START MODE 失效
公开(公告)号：JPS60253331A
公开(公告)日：1985-12-14
申请号：JP10991284
申请日：1984-05-30
申请人： FUJITSU LTD
发明人： YAMADA HIROSHI , AOKI KOUJI , WATANABE NAOKI
IPC分类号： H04B3/04
摘要： PURPOSE:To equalize the circuit distortions regardless of variation of the transmission characteristics in an MODEM by equalizing the distortions within the MODEM with return of own station to store the equalization value as the initialization value and starting the automatic equalization and the control of an automatic phase control circuit for the circuit distortions based on said initialization value. CONSTITUTION:Switches SW1 and SW2 are set at the dotted line sides for return at own station in order to equalize the distortions within an MODEM before the circuit distortions are equalized by the MODEM. In this case, the initialization value of the center value of a dynamic range is given previously to up/down counters 19, 23 and 27 from RAM29-31. Then the equalization is carried out, and the values of counters 19, 23, 27 are stored in RAM29-31 as the result of equalization. Then switches SW1 and SW2 are changed to the solid line sides to secure the actuation of the MODEM. In this case, the values stored in RAM29-31 are given to counters 19, 23, 27 as the initial values. Then the circuit distortions are equalized from the value obtained by equalizing the distortions within the MODEM. Therefore, a large distortion does not suddenly produce when the working is started.

6. 发明专利

JPS60194840A Performance check system of modem 失效
标题翻译：调制解调器性能检查系统
公开(公告)号：JPS60194840A
公开(公告)日：1985-10-03
申请号：JP5193284
申请日：1984-03-16
申请人： Fujitsu Ltd
发明人： AOKI KOUJI , YAMADA HIROSHI , IKUTA KOUJI , WATANABE NAOKI
IPC分类号： H04B3/04 , H04L1/20 , H04L27/00
CPC分类号： H04L1/206
摘要： PURPOSE:To attain ease of performance check as required by generating a random disturbing pattern signal, summing the signal at an input point of an automatic equalizer waveform-shaping a digital signal to check an erroneous pulse in an output pulse of the automatic equalizer. CONSTITUTION:An analog normal signal (1) is inputted and inputted to an adder 9 via a reception LPF4 after A/O conversion 5. On the other hand, a binary random pattern is generated (7) and a disturbing signal (2) symmetrical in both polarity is generated by a variable coefficient device 8 and the result is outputted to an adder 9. The adder 9 adds digitally the signals (1) and (2) and gives the result to a register 10 while being shifted sequentially. After data of the register 10 is operated by a multiplier/adder 11 together with an output of a coefficient device 12, a polarity error and an error bit are discriminated by a discriminator 14, the degree of correlation of the state of generation is generated (13), the corresponding coefficient is generated (12), multiplied/added (11) and the result is outputted to a discriminator 14. An unnecessary pulse component is eliminated from an output signal of the discriminator 14 and the result is outputted as a reproducing signal. Thus, the performance of an MODEM is checked simply by operating a variable coefficient device 8.
摘要翻译：目的：为了通过产生随机扰动模式信号来实现所需的性能检查的容易性，对自动均衡器波形的数字信号的输入点处的信号求和，以检查自动均衡器的输出脉冲中的错误脉冲。构成：模拟正常信号（1）在A / O转换5之后通过接收LPF4输入并输入到加法器9.另一方面，产生二进制随机模式（7）和干扰信号（2）对称两极性都由可变系数器件8产生，结果被输出到加法器9.加法器9以数字方式加上信号（1）和（2），并将结果顺序移位给寄存器10。在乘法器/加法器11与系数器件12的输出一起操作寄存器10的数据之后，鉴别器14鉴别出极性误差和误差位，产生状态的相关程度（生成（12），相加/相加（11）相应的系数，并将结果输出到鉴别器14.从鉴别器14的输出信号中消除不必要的脉冲分量，并将结果输出为再现信号。因此，简单地通过操作可变系数装置8来检查MODEM的性能。

7. 发明专利

JPS5974755A Test system of data circuit 失效
标题翻译：数据电路测试系统
公开(公告)号：JPS5974755A
公开(公告)日：1984-04-27
申请号：JP18497882
申请日：1982-10-20
申请人： Fujitsu Ltd
发明人： AOKI KOUJI , YAMADA HIROSHI , IKUTA KOUJI , WATANABE NAOKI
IPC分类号： H04L25/02 , H04B17/40
CPC分类号： H04B17/403
摘要： PURPOSE:To improve the transmission efficiency and to reduce the cost of a data circuit, by checking the circuit only by an operator of the transmitting station side. CONSTITUTION:At a transmitting station 1; a preparation signal generator 111, address designation signal generator 112 for designation of the receiving station, pattern generator 12 which generates a test signal and release signal generator 113 are distributed so that an output can be delivered to a data circuit D via a transmission input changeover switch 10 and a transmitter 11. At the same time, level detectors 114, 116, etc. are provided for each order wire to the order wire terminals set between receiving stations 2-3. A preparation signal discriminator 211, address designation discriminator 212, pattern collator 22 and a release signal discriminator 213 are set at stations 2-3 respectively so as to work in response to the output of a receiver 21. The output of the collator 22 is connected to an order wire OW1 via a level controller 214 which controls the transmission level of a pilot signal generator 215.
摘要翻译：目的：为了提高传输效率，降低数据电路的成本，仅通过发送站侧的操作者检查电路。构成：在发射台1; 分配准备信号发生器111，用于指定接收站的地址指定信号发生器112，产生测试信号的模式发生器12和释放信号发生器113，以便可以通过传输输入切换将输出传送到数据电路D 开关10和发送器11.同时，为设置在接收站2-3之间的订单线端子的每个订单线提供电平检测器114,116等。准备信号鉴别器211，地址指定鉴别器212，模式校正器22和释放信号鉴别器213分别设置在站2-3处，以便响应于接收机21的输出工作。校准器22的输出被连接通过控制导频信号发生器215的发送电平的电平控制器214连接到订单线OW1。

8. 发明专利

JPH04124932A SECRET PROTECTIVE COMMUNICATION SYSTEM 失效
公开(公告)号：JPH04124932A
公开(公告)日：1992-04-24
申请号：JP24650890
申请日：1990-09-17
申请人： FUJITSU LTD
发明人： WATANABE NAOKI
IPC分类号： H04L9/34 , H04L9/28 , H04L9/36
摘要： PURPOSE:To keep a secret through a simple and inexpensive method by providing a transmitting side with a data shifting part to shift data by M-bits between a coding part and a multiplexing part, and providing a receiving side with a frame shifting part to shift a frame bit by M-bits between a demultiplexing part and a decoding part. CONSTITUTION:At the transmitting side, the data of n-bits is shifted by M-bits from the frame bit by the data shifting part 5, and is inputted to the multiplexing part 2, and it is multiplexed with the frame bit by the multiplexing part 2, and is transmitted, and at the receiving side, the frame bit and the data of n-bits are separated by the demultiplexing part 3, and the data of n-bits is inputted to the decoding part 4, and the frame bit is shifted by M-bits by the frame shifting part 6, and is inputted to the decoding part 4, and at the decoding part 4, decoding is executed on the basis of the frame bit shifted by M-bits. Since the decoding based on the frame bit can not be executed, the secret is kept.

9. 发明专利

JPS59225620A SWITCHING METHOD OF MODULATOR-DEMODULATOR 失效
公开(公告)号：JPS59225620A
公开(公告)日：1984-12-18
申请号：JP10110283
申请日：1983-06-07
申请人： FUJITSU LTD
发明人： AOKI KOUJI , YAMADA HIROSHI , IKUTA KOUJI , WATANABE NAOKI
IPC分类号： H04L27/00 , H04B1/00
摘要： PURPOSE:To improve the data transmission efficiency by changing a bit rate of data so as to transmit the data at all voice frequency bands when no voice is transmitted, changing also the modulating frequency at the same time, and allowing the reception side to detect this change and the mode to be changed over into the data reception mode. CONSTITUTION:When no voice is transmitted, switches SW1-SW3 are thrown to the position shown in dotted line manually at the transmission side. When the switch SW1 is connected to the position in dotted lines, a clock having a frequency of four times is applied to a code converter 1, a base band digital filter 2, a modulator 3 and a carrier band digital filter 4 from a clock generator 20 generating the clock having the frequency four times that of a clock generator 9 so as to allow the code converting circuit 1 to binary-code binary data in a speed four times that of the transmission of voice and data. Thus the data having a transmission speed of four times that of the transmission of voice and data is received. The carrier of data being an output of the filter 4 uses all voice frequency bands. The receiving side discriminates the transmission of only data by means of the received carrier and changes over the mode into a discrimination output data reception mode.

10. 发明专利

JPS59119947A TRANSMISSION SYSTEM OF PARTIAL RESPONSE 失效
公开(公告)号：JPS59119947A
公开(公告)日：1984-07-11
申请号：JP22835082
申请日：1982-12-27
申请人： FUJITSU LTD
发明人： AOKI KOUJI , YAMADA HIROSHI , IKUTA KOUJI , WATANABE NAOKI
IPC分类号： H04L25/497
摘要： PURPOSE:To facilitate easy detection of a code error at the reception side and to attain an automatic correction of the code error, by inserting a frame pattern using a code which causes an error by the inversion of signal to an input signal at the transmission side. CONSTITUTION:The speed of an input signal is converted by a speed converting circuit 7 at the transmission. A frame pattern using a code which causes an error by the inversion of signal is inserted to the input signal by a frame pattern inserting circuit 8. This inserted pattern is transmitted via a partial response coder 1. At the reception side, the synchronism is obtained between two frame patterns, i.e., the outputs of a partial response decoder 6 by a frame synchronous circuit 9, to detect whether the frame pattern is inverted. If the frame pattern is inverted, the code error is corrected by an inversion correcting circuit 11. Then the frame pattern is deleted by a speed converting circuit 12 to obtain the original signal.

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