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1. 发明专利

JPH04155560A INPUT/OUTPUT CONTROL SYSTEM 失效
公开(公告)号：JPH04155560A
公开(公告)日：1992-05-28
申请号：JP28137490
申请日：1990-10-19
申请人： FUJITSU LTD
发明人： ODAKAWA TOSHIYUKI
IPC分类号： G06F13/14 , G06F13/00
摘要： PURPOSE:To automatically detect a faulty part in the path of a control line by outputting one bit signal since a selection signal is outputted from a channel device until an input/output control device starts operating, and detecting the generation of an abnormality when a signal indicating an operation is not responded from any input/output control device. CONSTITUTION:A channel device 1 transmits through the address bus of an input/output device 2' to each input/output control device, and transmits the selection signal from a selection signal line 9. A state detecting part 5 detects the period since the selection signal is outputted from the channel device 1 until the input/output control devices 2 and 2' are selected and starts operating, in the meantime the one bit signal is transmitted from a selection signal confirming part 6 to a data bus. When an operation indicating signal indicating a selection is not returned from any input/output control device, based on the one bit signal on the data bus transmitted from each input/output control device, it is confirmed how far the selection signal is transferred. Thus, it is possible to automatically detect the input/output control device with the fault, when the fault is generated in the path of the selection signal line.

2. 发明专利

JPS62165256A DATA TRANSFER SYSTEM OF COMMUNICATION CONTROL PROCESSOR 失效
公开(公告)号：JPS62165256A
公开(公告)日：1987-07-21
申请号：JP742786
申请日：1986-01-17
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , ODAKAWA TOSHIYUKI , NOMOTO KAORU
IPC分类号： G06F13/00 , G06F13/38
摘要： PURPOSE:To improve the efficiency of data transfer between a communication control processor and a host channel by monitoring the last address bit of a buffer and a transfer stop bit by a monitor part in a data transfer control part. CONSTITUTION:A data buffer 110 which is provided on a control storage 11 and consists of two faces (A and B), buffer last address bits 111 in table areas (A and B) 110' provided for the data buffer 110, transfer stop bits 112, and a monitor part 132a which monitors buffer last address bits 111 and transfer stop bits 112 in a data transfer control part 132 are provided. Two data buffers are provided on the control storage, and bits indicating the last addresses and transfer stop bits are monitored each time data is transferred to the channel once, and use states of data buffers are decided to execute simultaneously the transfer operation to the channel and the cycle steal operation. Thus, the efficiency of data transfer between the communication control processor and the host channel is improved.

3. 发明专利

JPS61294566A COMMUNICATION CONTROL PROCESSOR 失效
公开(公告)号：JPS61294566A
公开(公告)日：1986-12-25
申请号：JP13739385
申请日：1985-06-24
申请人： FUJITSU LTD
发明人： SATO KIYOSHI , ODAKAWA TOSHIYUKI , HIWATARI AKITO
IPC分类号： H04L29/04 , G06F13/00 , H04L13/00
摘要： PURPOSE:To perform the sense/control operation with various transistors without using any special interface by performing the reading/writing operations of various registers set at circuit junction parts in an invalid mode where no request is given to the bit processing. CONSTITUTION:In a sense mode a sense/control indication, the sense and a register address are written to a desired circuit corresponding memory (ICW)10. A circuit junction part LiC sets the contents of the register indicated by a register address given from an out-bus to an in-bus. Then a circuit scan part CS writes the data to the ICW10. While in a control mode a sense/control indication, the control and the register address setting data to the desired ICW10. The part LiC receives a register address and data from the out-bus and sets this data to the register indicated by the register address.

4. 发明专利

JPS61131048A Memory access controlling system 失效
标题翻译：存储器访问控制系统
公开(公告)号：JPS61131048A
公开(公告)日：1986-06-18
申请号：JP24761984
申请日：1984-11-22
申请人： Fujitsu Ltd
发明人： TAKAHASHI HIROSHI , OGAWA YOSHIHISA , ODAKAWA TOSHIYUKI
IPC分类号： G06F11/10 , G06F12/16
摘要： PURPOSE: To reduce the number of buffers, etc., required for controlling memory access, by performing correction by transferring the content of a master register to a slave register when the error of the data of the master register is corrected.
CONSTITUTION: The master register 8 is used as a register for holding data to be inputted in and outputted from a memory device 1 and a slave register 9 is used as an instruction buffer which holds the instruction to be executed next. Data read out to the register 8 for partial writing are checked for error at an ECC circuit 12. When a correctable error is detected, the ECC circuit 12 controls an FF circuit 7 to transfer the content of the master register 8 to the slave register 9 and switches the input to the ECC circuit 12 to the register 9 side. The ECC circuit 12 executes correcting processes to the input from the register 9 and sets the corrected data in the register 8.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了减少控制存储器访问所需的缓冲器数量，通过在校正主寄存器的数据的错误时，通过将主寄存器的内容传送到从属寄存器进行校正。构成：主寄存器8用作用于保存要从存储器件1输入并从存储器件1输出的数据的寄存器，并且从寄存器9用作保持接下来要执行的指令的指令缓冲器。在ECC电路12处检查用于部分写入的寄存器8的数据读出错误。当检测到可校正错误时，ECC电路12控制FF电路7将主寄存器8的内容传送到从寄存器9 并将输入切换到ECC电路12到寄存器9侧。 ECC电路12对来自寄存器9的输入执行校正处理，并将校正数据设置在寄存器8中。

5. 发明专利

JPS61123241A Polling control system 失效
标题翻译：巡检控制系统
公开(公告)号：JPS61123241A
公开(公告)日：1986-06-11
申请号：JP23606184
申请日：1984-11-09
申请人： Fujitsu Ltd
发明人： OKADA TATSUO , TAKAHASHI HIROSHI , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE: To improve the reliability of communication processing by allowing a sub channel controlling transmission to start a timer monitoring reception of reply information through a sub channel controlling the reception every time polling for one destination is finished.
CONSTITUTION: A polling command is issued to a required transmission sub channel from a CPU 2 via a line control part. A transmission sub channel LCW#i subject to polling command transmits polling control information to its destination. When the transmission is finished, a main control part 7 is interrupted. The main control part 7 is starts a timer to monitor a reply signal caused by a #i reception sub channel of an LCW 6 in pairs of a #i transmission sub channel. When the line control section 3 detects timeout, communication information is set to the notice area of the corresponding local storage LS 9. Then one cycle of the polling is finished and the next polling command is started. Thus, the reliability of communication processing is improved and the utilizing efficiency of a communication line is improved.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了提高通信处理的可靠性，通过允许子信道控制传输，通过每次轮询一个目的地完成控制接收的子信道来启动定时器监视应答信息的接收。构成：通过线路控制部件从CPU 2向所需的发送子信道发出轮询命令。进行轮询命令的发送子信道LCW＃i向其目的地发送轮询控制信息。当传输完成时，主控制部分7被中断。主控制部分7启动定时器以监视由#i发送子信道成对的LCW 6的#i接收子信道引起的应答信号。当线路控制部分3检测到超时时，通信信息被设置到对应的本地存储器LS 9的通知区域。然后完成轮询的一个周期并且开始下一个轮询命令。因此，提高通信处理的可靠性，提高通信线路的利用效率。

6. 发明专利

JPS6058748A COMMUNICATION CONTROL AND PROCESSING SYSTEM 失效
公开(公告)号：JPS6058748A
公开(公告)日：1985-04-04
申请号：JP16690583
申请日：1983-09-10
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , TAKAHASHI HIROSHI , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/04 , H04L12/52
摘要： PURPOSE:To relieve the load of program processing and also to realize the simplicity of the program by accessing directly to a procedure storage means storing information of transmission control procesure obtained based on the state information of a line including a state management data to know the attribute of line and the state transition of line and a transmission/reception data before a processing request is generated from a line corresponding section. CONSTITUTION:A reception data inputted from a reception data line in a prescribed communicatiin speed is set and shifted to a shift register 233a one by one bit at reception operation and transmitted to a register 234a at each 8-bit. A processing request is generated to a processing function CC20a and the processing method of the reception data in a register 234a is decided according to a control data CD in a register 235a. A transmission data is set to a register 234b from the CC20a in the transmission operation and the data is transmitted one by one bit from a shift register, and except these processings, a transmission control section 23ba is operated so as to input/output the data same as the reception operation in other circuits, character classification codes CTB, CD, medium control sequence information CTB, CD and medium sequence information PSQ are read and the processing is repeated.

7. 发明专利

JPS5979348A Register circuit 失效
标题翻译：寄存器电路
公开(公告)号：JPS5979348A
公开(公告)日：1984-05-08
申请号：JP19039782
申请日：1982-10-29
申请人： Fujitsu Ltd
发明人： ODAKAWA TOSHIYUKI , OGAWA YOSHIHISA , TAKAHASHI HIROSHI
IPC分类号： G06F7/00 , G01R31/3185
CPC分类号： G01R31/318547
摘要： PURPOSE:To obtain a shift register circuit which is capable of scan-in/scan-out operations to the data used for a scan-in operation without being aware of a parity bit, by providing a means to generate automatically a desired parity bit. CONSTITUTION:When a scan control signal SCS is set at logic 0, and FF circuit AP is cut off and the data containing no parity bit corresponding to the data bits of FF circuits A0, A1-A7 is shifted. In this case, a parity bit producing function of an exclusive OR circuit EOR is actuated and this output is applied to the circuit AP. With this operation, the EOP discriminates three signals to be supplied and sets even parities to the circuits A0-A7 as long as the parity is assured in the previous records of the circuits A0-A7 and the circuit AP or all FFs are initialized by zero resetting. Therefore, an even parity is always assured at each step of a shift operation. In this case, however, the data is limited to 8 bits with the circuits A0-A7.
摘要翻译：目的：通过提供自动生成所需奇偶校验位的手段，获得能够扫描输入/扫描输出操作的移位寄存器电路，用于扫描操作中使用的数据，而不需要知道奇偶校验位。构成：当扫描控制信号SCS设置为逻辑0时，FF电路AP被切断，并且不包含与FF电路A0，A1-A7的数据位相对应的奇偶校验位的数据被移位。在这种情况下，启动异或电路EOR的奇偶校验位产生功能，并且该输出被施加到电路AP。通过该操作，只要在电路A0-A7和电路AP的先前记录中保证奇偶校验或者将所有FF初始化为零，EOP就鉴别要提供的三个信号并将均匀的奇偶校验设置到电路A0-A7 复位。因此，在换档操作的每个步骤中始终保证偶校验。然而，在这种情况下，电路A0-A7将数据限制为8位。

8. 发明专利

JPS56154851A CIRCUIT SCANNING SYSTEM 失效
公开(公告)号：JPS56154851A
公开(公告)日：1981-11-30
申请号：JP5764880
申请日：1980-04-30
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , SADAKUNI YUUJI , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
摘要： PURPOSE:To increase processing performance by eliminating the time of an ineffective scan by selecting a circuit group with the highest priority level among respective groups during a circuit scan by dividing circuits, differing in communication rate, into groups and by previously storing the top priority processing circuit number for requests for processing. CONSTITUTION:Circuit coordinating circuits 21 of circuits differing in communication rate are divided into the 1st-(n)-th groups; and storage 10 for a table is provided previously with areas for the 1st group the (n)-th group and in each area, an in-group circuit number, priority level specifying information, in-group circuit number effective specifying information, and final-group specifying information are inputted from signal line 16 and stored. During a scan, a request-for-processing signal from each group is applied to address register 11 for the table via request-for- processing signal line 18 and on the basis of its address, access to storage 10 is attained to select the in-group top-priority circuit in every group by utilizing buffer register 14 for comparison. Further, the top-priority circuits in respective groups are compared mutually to select single circuit 21 with the highest priority level, thereby increasing the processing performance.

9. 发明专利

JPH01255932A INSTRUCTION PROCESSOR 失效
公开(公告)号：JPH01255932A
公开(公告)日：1989-10-12
申请号：JP8375888
申请日：1988-04-05
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , ODAKAWA TOSHIYUKI
IPC分类号： G06F9/38 , G06F13/00 , G06F13/12
摘要： PURPOSE:To shorten instruction processing time by predicting an introduced instruction, executing a precedence processing, and when the prediction is wrong, executing the processing in accordance with the introduced instruction. CONSTITUTION:A first processing means to execute the processing in accordance with a prescribed instruction introduced successively executes the precedence processing in accordance with the predictive result. A deciding means 131 decides whether or not the prediction by a predictive means 111 is right and the decided result is supplied to a second processing means 141. When the predictive result by the predictive means 111 is wrong, the second processing means 141 executes the processing in accordance with the introduced instruction. Thus, since the instruction introduced is predicted and the precedence processing is executed, instruction processing time can be shortened.

10. 发明专利

JPH01121924A DATA TRANSFER DEVICE 失效
公开(公告)号：JPH01121924A
公开(公告)日：1989-05-15
申请号：JP27907187
申请日：1987-11-06
申请人： FUJITSU LTD
发明人： ODAKAWA TOSHIYUKI
IPC分类号： G06F5/06
摘要： PURPOSE:To improve the efficiency of data transfer by reading out data from a data buffer, in which data transferred from a first interface is stored, while dividing this data based on stored division information and transferring data to a second interface. CONSTITUTION:Data transferred from a first interface 1 is written in a data buffer 2. A control means 4 controls the transfer operation, where data is read out from the data buffer 2 while being divided to transfer divided data to a second interface 6, and the transfer stop operation. Divided data is quickly transferred in this manner to improve the efficiency of data transfer.

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