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1. 发明专利

JPS62165256A DATA TRANSFER SYSTEM OF COMMUNICATION CONTROL PROCESSOR 失效
公开(公告)号：JPS62165256A
公开(公告)日：1987-07-21
申请号：JP742786
申请日：1986-01-17
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , ODAKAWA TOSHIYUKI , NOMOTO KAORU
IPC分类号： G06F13/00 , G06F13/38
摘要： PURPOSE:To improve the efficiency of data transfer between a communication control processor and a host channel by monitoring the last address bit of a buffer and a transfer stop bit by a monitor part in a data transfer control part. CONSTITUTION:A data buffer 110 which is provided on a control storage 11 and consists of two faces (A and B), buffer last address bits 111 in table areas (A and B) 110' provided for the data buffer 110, transfer stop bits 112, and a monitor part 132a which monitors buffer last address bits 111 and transfer stop bits 112 in a data transfer control part 132 are provided. Two data buffers are provided on the control storage, and bits indicating the last addresses and transfer stop bits are monitored each time data is transferred to the channel once, and use states of data buffers are decided to execute simultaneously the transfer operation to the channel and the cycle steal operation. Thus, the efficiency of data transfer between the communication control processor and the host channel is improved.

2. 发明专利

JPS61153746A INTERRUPTION CONTROLLING SYSTEM OF COMMUNICATION CONTROL PROCESSOR 失效
公开(公告)号：JPS61153746A
公开(公告)日：1986-07-12
申请号：JP27685584
申请日：1984-12-27
申请人： FUJITSU LTD
发明人： NOMOTO KAORU , SATO KIYOSHI , TAKAHASHI HIROSHI
IPC分类号： H04L29/02 , G06F13/00 , G06F13/10 , G06F13/24
摘要： PURPOSE:To reduce an ineffective waiting time of a processing part, and to shorten the processing time by utilizing a response waiting time of the time when executing an input/output instructon, and executing the processing of other program level. CONSTITUTION:A title device is provided with a level 1 inhibiting FF13 which is set by AND of a level 1 running signal 21 and an input/output instruction executing signal 19, and reset by an input/output instruction completing signal 20 from an adaptor. Also, it is constituted so that AND of an output of a level 1 signal holding FF11 for holding a level 1 signal 17 from the adaptor, and a logical inverting signal of the level 1 inhibiting FF13 becomes a level 1 inpt logic of an interruption controlling circuit 10. In this way, when an input/output instruction is executed in the course of running of a level 1, the level 1 signal is inhibited. At that time, if a level 2 whose priority order is low is requested, a level 2 runs, and it is reset to the level 1, when a type 1 adaptor issues an input/output instruction completing signal.

3. 发明专利

JPS61153750A COMMON BUS CONTROL SYSTEM 失效
公开(公告)号：JPS61153750A
公开(公告)日：1986-07-12
申请号：JP27685684
申请日：1984-12-27
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO , SATO KIYOSHI , NOMOTO KAORU
IPC分类号： G06F13/362 , G06F13/364
摘要： PURPOSE:To improve the throughput of a data transfer by constituting a title system so that a device which has obtained a common bus using right once holds the bus using right until it receives a common bus using request from other device. CONSTITUTION:A channel adaptor (CA)3 sets a bus using request display flip- flop (BRQ FF)15, and sends out a bus using request signal (BRQ)21 to a commonn bus control part 4. The common bus control part 4 decides the BRQ from each device, returns a bus use permitting singal (BACK)22 to one selected device, and also sets a bus busy display flip-flop (BBSY FF)12. In the CA which has generated the BRQ21, when a bus aquisition and storage use flip-flop (BHLD FF)14 is set already, its BHLD FF14 is not reset.

4. 发明专利

JPS61128342A Serial scan control system 失效
标题翻译：串行扫描控制系统
公开(公告)号：JPS61128342A
公开(公告)日：1986-06-16
申请号：JP25092184
申请日：1984-11-28
申请人： Fujitsu Ltd
发明人： OGAWA YOSHIHISA , NOMOTO KAORU , SATO KIYOSHI
IPC分类号： G06F11/22 , G06F11/267
CPC分类号： G06F11/2236
摘要： PURPOSE:To improve the efficiency of processing by dividing a shift register into plural shift register so as to shift data individually and forming a course transferring data in parallel between these shift registers. CONSTITUTION:The shift register for input data is constituted of a data register 20, a transferred address specifying register 21 and a control register 22. Another data register is formed to hold read data. When writing is to be accessed to a control storage device 1, input data are shifted and inputted from an input terminal 8 and set up in the registers 20-22, the contents of the registers 20-22 are transferred to an address register 2 and a data register 3 and then the data are written in the device 1 on the basis of the contents of the registers 2, 3. In case of reading access, transferred address specification and reading access specification are shifted and inputted from the input terminal 8 and the device 1 executes reading operation and sets up the data in the register 24. The contents of the register 24 are shifted and outputted to an output terminal to output the reading data.
摘要翻译：目的：通过将移位寄存器分为多个移位寄存器来提高处理效率，以便单独移位数据，并在这些移位寄存器之间形成并行传输数据的过程。构成：用于输入数据的移位寄存器由数据寄存器20，传送地址指定寄存器21和控制寄存器22构成。形成另一个数据寄存器来保存读取数据。当写入要被访问到控制存储设备1时，输入数据从输入端子8移位并输入并设置在寄存器20-22中，寄存器20-22的内容被传送到地址寄存器2和数据寄存器3，然后基于寄存器2,3的内容将数据写入设备1.在读取访问的情况下，传送的地址指定和读取访问规范从输入端子8移位和输入，设备1执行读取操作并将数据设置在寄存器24中。寄存器24的内容被移位并输出到输出端以输出读取数据。

5. 发明专利

JPS61128331A Data transfer control system 失效
标题翻译：数据传输控制系统
公开(公告)号：JPS61128331A
公开(公告)日：1986-06-16
申请号：JP25091884
申请日：1984-11-28
申请人： Fujitsu Ltd
发明人： ODAKAWA TOSHIYUKI , OGAWA YOSHIHISA , NOMOTO KAORU
IPC分类号： G06F13/38 , G06F5/06
摘要： PURPOSE: To update the large part of supervisory processing for receiving data length by a multiple of once and to improve the economical efficiency of a data transfer circuit by setting up the data length to the multiple of buffer length and holding fraction data length less than the buffer length.
CONSTITUTION: Data from one device is inputted to a buffer 2 in a data transmission control system through a data line 1 and transmitted to the other device through a data line 3. The data transmission is controlled by an address resister 4, a difference detecting counter 8 and and address register 9. The quantient obtained by dividing an integer by the number of bytes of the buffer 2 is defined as the buffer multiple and the residual is defined as the fraction data length. The buffer multiple is loaded to a memory in a microprocessor 21 and the fraction data length is set up previously in a register 20. A comparator 22 always compares the contents of the registers 4, 20 and the processor 21 is interrupted by a carry signal 24 from the register 4. Thus, the large part of the supervisory processing of the data length is updated by the multiple of once and the operation of the data transfer circuit is simplified.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了更新接收数据长度一次的大部分监控处理，通过将数据长度设置为缓冲长度的倍数和保持分数数据长度小于数据长度，提高数据传输电路的经济性缓冲区长度。构成：通过数据线1将来自一个设备的数据输入到数据传输控制系统中的缓冲器2，并通过数据线3被传送到另一个设备。数据传输由地址寄存器4，差分检测计数器 8和地址寄存器9.通过将整数除以缓冲器2的字节数获得的量子被定义为缓冲器倍数，并且残差被定义为分数数据长度。缓冲器倍数被加载到微处理器21中的存储器中，并且分数数据长度被预先设置在寄存器20中。比较器22总是比较寄存器4,20的内容，并且处理器21被进位信号24中断因此，数据长度的大部分监视处理被更新一次，并且数据传送电路的操作被简化。

6. 发明专利

JPH0368587B2 失效
公开(公告)号：JPH0368587B2
公开(公告)日：1991-10-29
申请号：JP15980285
申请日：1985-07-19
申请人： FUJITSU LTD
发明人： HIWATARI AKITO , KISHI MASAHIRO , NOMOTO KAORU
IPC分类号： H04L25/40 , H04L7/04 , H04L13/00 , H04L29/00 , H04L29/04 , H04L29/08 , H04L29/10

7. 发明专利

JPS61272853A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS61272853A
公开(公告)日：1986-12-03
申请号：JP11580585
申请日：1985-05-29
申请人： FUJITSU LTD
发明人： NOMOTO KAORU , OGAWA YOSHIHISA , KIMURA YOSHIHIRO
IPC分类号： G06F13/38 , G06F13/00 , H04L13/00 , H04L29/02
摘要： PURPOSE:To improve the capacity of processing by constituting so as to realize the arranging operation of transferred bytes independently of byte width of the second storage means when transferring the data from the first storage means to the second storage means. CONSTITUTION:When storing the data received by a transmission/receiving controlling section 6 in a controlling memory 5, the same data are stored in two receiving data buffers 13, 14 from positions different by 1 byte. That is, the address of received data buffer (1) 13 side is prepared by the output of a data buffer register 11 as the address on bisected controlling memories 5 (5-1, 5-2), and the address of a received data buffer (2) 14 side is prepared by the output of a +1 adder circuit 12 for renewing the data buffer register 11. The 5-1 side of the highest bit is controlled to logic '0', and 5-2 side is controlled to logic '1' when accessing controlling memories 5 (5-1, 5-2).

8. 发明专利

JPS61101143A Line scanning system 失效
标题翻译：线扫描系统
公开(公告)号：JPS61101143A
公开(公告)日：1986-05-20
申请号：JP22324184
申请日：1984-10-24
申请人： Fujitsu Ltd
发明人： OGAWA YOSHIHISA , TAKAHASHI HIROSHI , HIWATARI AKITO , SATO KIYOSHI , NOMOTO KAORU
IPC分类号： H04L29/04 , H04L13/00
摘要： PURPOSE: To improve the processing capability of the system by providing a line scanning register, a line scanning section and a line control section to a line control adaptor and organizing a scanning loop to only an effective line used actually in a communication control processor comprising a main control section and plural line control adaptors.
CONSTITUTION: A scanning loop designating the order of scanning of lines through plural effective lines only designated for the use by the main control section 2 based on a start/release command of the line from a CPU is formed to scan corresponding lines in lines 10, 11' and line adaptors 9, 9' sequentially. A line control section 6 informs the line scanning number of the line commanded by the main control section 2 to a line scanning section 8, which registers the line scanning number to the scanning loop or releases it from the scanning loop based on the command. Further, a control memory 7 has a cut point of the scanning loop, that is, a head final scanning number being an inserted point in registering newly the line. Thus, in registering a line, the final line number is revised.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过向线路控制适配器提供线扫描寄存器，线扫描部分和线路控制部分，并将扫描循环仅组织到实际上在通信控制处理器中使用的有效线，以提高系统的处理能力，该通信控制处理器包括主控部分和多条线控制适配器。构成：通过基于来自CPU的行的开始/解除命令，仅指定为主控制部2使用的多条有效行的行扫描顺序的扫描回路，扫描行10， 11'和线适配器9,9'。行控制部6将由主控制部2指令的行的行扫描次数通知行扫描部8，该行扫描部8基于该命令将行扫描次数登记到扫描循环或将其从扫描循环释放。此外，控制存储器7具有扫描循环的切割点，即，头部最终扫描次数是新记录的插入点。因此，在注册一行时，修改最后的行号。

9. 发明专利

JPS6220448A BIT SAMPLING SYSTEM 失效
公开(公告)号：JPS6220448A
公开(公告)日：1987-01-29
申请号：JP15980285
申请日：1985-07-19
申请人： FUJITSU LTD
发明人： HIWATARI AKITO , KISHI MASAHIRO , NOMOTO KAORU
IPC分类号： H04L25/40 , H04L7/04 , H04L13/00 , H04L29/00 , H04L29/04 , H04L29/08 , H04L29/10
摘要： PURPOSE:To prevent the failure in sampling of reception bits without advance sampling by providing a means which reports it to a line connection part that a sampling control circuit recognizes the change of reception data reported from the line connection part. CONSTITUTION:This system is so constituted that a reception data change detection signal (RDCM) 10 is sent to a line connection part (LA) 2. With respect to the sample in a reception bit sampling register (RDB) 15, the value of the reception bit sampling register (RDB) 15 at the preceding sampling time is held and is transmitted to a line control part (LNCT) 3 when a reception data change detection signal (RDCM) 10 from a control circuit (SPC) 1 is turned on.

10. 发明专利

JPS6171746A Communication control equipment 失效
标题翻译：通讯控制设备
公开(公告)号：JPS6171746A
公开(公告)日：1986-04-12
申请号：JP19368584
申请日：1984-09-14
申请人： Fujitsu Ltd
发明人： HIWATARI AKITO , SATO KIYOSHI , NOMOTO KAORU
IPC分类号： H04L29/04 , H04L13/00
CPC分类号： H04L13/00
摘要： PURPOSE:To reduce the generation of character overrun by using a line memory area of a line not scanned through the limit of a scanning address range as the buffer of a line memory area of a scanned line. CONSTITUTION:An address correction circuit 21 constituted by signals (character composition end signal SVC, processing request storage bit MSUR, overrun storage bit MOVR etc.) used by a conventional system is added. Thus, if the scanning address range is limited, an area not scanned by a line memory LM, that is, part B in figure is used as a scanned line memory area, that is, a buffer of the A. Further, the part B is a simple buffer, to which the data in the part A is transmitted by the said SVC-ON, MSVR-ON, MOVR-OFF and no character composition is executed, then the control is attained.
摘要翻译：目的：通过使用未扫描扫描地址范围限制的行的行存储区域作为扫描行的行存储区域的缓冲区，减少字符溢出的产生。构成：添加由常规系统使用的信号（字符组合结束信号SVC，处理请求存储位MSUR，超限存储位MOVR等）构成的地址校正电路21。因此，如果扫描地址范围受到限制，则将未被行存储器LM扫描的区域，即图中的部分B用作扫描行存储区域，即A的缓冲区。此外，部分B 是一个简单的缓冲器，通过所述SVC-ON，MSVR-ON，MOVR-OFF传送部分A中的数据，并且不执行字符组成，然后获得控制。

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