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1. 发明专利

JPS56154851A CIRCUIT SCANNING SYSTEM 失效
公开(公告)号：JPS56154851A
公开(公告)日：1981-11-30
申请号：JP5764880
申请日：1980-04-30
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , SADAKUNI YUUJI , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
摘要： PURPOSE:To increase processing performance by eliminating the time of an ineffective scan by selecting a circuit group with the highest priority level among respective groups during a circuit scan by dividing circuits, differing in communication rate, into groups and by previously storing the top priority processing circuit number for requests for processing. CONSTITUTION:Circuit coordinating circuits 21 of circuits differing in communication rate are divided into the 1st-(n)-th groups; and storage 10 for a table is provided previously with areas for the 1st group the (n)-th group and in each area, an in-group circuit number, priority level specifying information, in-group circuit number effective specifying information, and final-group specifying information are inputted from signal line 16 and stored. During a scan, a request-for-processing signal from each group is applied to address register 11 for the table via request-for- processing signal line 18 and on the basis of its address, access to storage 10 is attained to select the in-group top-priority circuit in every group by utilizing buffer register 14 for comparison. Further, the top-priority circuits in respective groups are compared mutually to select single circuit 21 with the highest priority level, thereby increasing the processing performance.

2. 发明专利

JPS55165054A FAILURE DETECTION UNIT IN COMMUNICATION CONTROL UNIT OF SYNCHRONIZING SYSTEM 失效
公开(公告)号：JPS55165054A
公开(公告)日：1980-12-23
申请号：JP7319279
申请日：1979-06-11
申请人： FUJITSU LTD
发明人： SADAKUNI YUUJI , HIHARA SEIJI
IPC分类号： H04L29/14 , H04L7/00
摘要： PURPOSE:To reduce the processing time and to enable to save the amount of hardware, by directly detecting the loss of the timing signal and informing it to the program. CONSTITUTION:In the signal read-in at the leading of the clock 1(1), the output of Q, Q' of FF3 is respectively as (3), (3)' and FF4 output is as (4). Further, the outputs (3)' and (4) are at ''H'' at the H and L switching point of the timing signal 2(2), and the output of the exclusive OR gate 5 is at ''0'' to reset the counter 6. On the other hand, when the signal 2 is fixed at ''H'' as shown in dotted lines, the output of the gate 5 is the state of ''1'', that is, the state without reset continues 4 clocks or more and the counter 6 overflows. That is, since the signal 2 is fixed at ''H'' or ''L'', the presence of the signal 2 can be detected quickly with the failure detection circuits 3-6. Next, the overflow output of the counter 6 is the failure check flag 10 via FF7 and interrupts the program with the character processing request flag 11.

3. 发明专利

JPS5696560A FAILURE PROCESSING SYSTEM IN COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS5696560A
公开(公告)日：1981-08-04
申请号：JP17319279
申请日：1979-12-28
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , SADAKUNI YUUJI
IPC分类号： H04L29/14 , G06F13/00 , G06F13/12
摘要： PURPOSE:To minimize the effect on terminal devices and to quickly check the cause to failure, by controlling the folding designation section so that the interface control signal for all the lines can be OFF with a failure detection output. CONSTITUTION:A control section 2 is started based on the microprogram of a memory 1, and the common control section transmits data on lines 0-n through time sharing multiplex control, then a failure detection section 2-1 detects the state impossible for the operation of program and transmits the detection signal to a state judging circuit 5. Thus, the circuit 5 sets FF6 to control the folding designation control circuit 9 and to turn off the line interface signal for line corresponding sections 10-0-10-N. Further, multiplexers 19, 20... are controlled to fold back the line interface signal among adjacent lines.

4. 发明专利

JPS5691564A TEST SYSTEM OF COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS5691564A
公开(公告)日：1981-07-24
申请号：JP16902479
申请日：1979-12-25
申请人： FUJITSU LTD
发明人： OGAWA YOSHIHISA , SADAKUNI YUUJI
IPC分类号： H04L29/14 , G06F13/00 , H04L12/26
摘要： PURPOSE:To shorten the test time of a communication controller by enabling it to test itself when a circuit control circuit is reset, not only by supplying a reset signal to the circuit control circuit, but also by operating the control circuit to discriminate its normalcy. CONSTITUTION:With a reset indication, FF5 turns on to reset the circuit. Next, the turning off of a data set ready DR and ready-for-sending CS signal is confirmed and then a data terminal ready ER and request-to-send RS signal is turned on to discriminate whether the DR and CS signal turns on a certain time later. After the DR and CS signal turns on, the ER and RS signal is turned off and further whether the DR and CS signal turns off a certain time later is discriminated. When the DR and CS signal is off, circuit scanning register 2 advances and said operation is performed repeatedly. When the said operation on the final circuit ends, reset indication FF5 is turned off and the self-testing operation is completed.

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