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1. 发明专利

JPH02245853A DATA PROCESSOR 失效
公开(公告)号：JPH02245853A
公开(公告)日：1990-10-01
申请号：JP6625489
申请日：1989-03-20
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO
IPC分类号： G06F11/34 , G06F11/00 , G06F13/00
摘要： PURPOSE:To facilitate trouble detection without increasing neither complicating hardware by stopping the operation of hardware, which controls the interface, to read in and record the state of this hardware at the time when a stop bit is set. CONSTITUTION:When a sequence table 13 is read out and a stop bit 13a is set, the operation of hardware which executes a microprogram is not stopped but the operation of a channel interface control part 12 which controls the interface is stopped hereafter. The stop of the operation of this hardware 12 is reported to a microprogram executing device, and the microprogram executing device reads in and records the state of the hardware 12 in the operation stop state of the hardware. Thus, trouble detection is facilitated without considerably increasing hardware.

2. 发明专利

JPS61294557A INSTRUCTION PROCESSOR 失效
公开(公告)号：JPS61294557A
公开(公告)日：1986-12-25
申请号：JP13739485
申请日：1985-06-24
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO , TAKAHASHI HIROSHI , SATO KIYOSHI
IPC分类号： G06F11/10 , G06F11/14
摘要： PURPOSE:To improve the instruction processing capacity of decoding and execut ing again a same instruction held by an instruction register via an ECC circuit in case the execution of an input/output instruction is not possible since the acquisition of a common bus is impossible. CONSTITUTION:The data read out of a memory MS1 is decoded by an instruction decoding circuit 5 and at the same time the 1-bit error is corrected by an ECC circuit 3 and held by an instruction register IR4. If an 1-bit error occurs here, the output data of the IR4 is decoded again by the circuit 5. Based on the decoding result, it is known that he instruction is equal to an input/output instruction using a common bus. However it is impossible to acquire the common bus. In such a case, the input/output instruction that is held by the IR4 and could not be executed is decoded and executed by the circuit 5 after the end of a cycle steal. This decreases the access frequency and improves the instruction processing capacity.

3. 发明专利

JPH0619718A PROGRAM LOADING SYSTEM 失效
公开(公告)号：JPH0619718A
公开(公告)日：1994-01-28
申请号：JP17829092
申请日：1992-07-06
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO
IPC分类号： G06F9/445
摘要： PURPOSE:To preserve a boot strap program(BSP) in a buffer memory(BFM) when it is loaded in a main storage(MS), to transfer BSP from BFM to MS in accordance with an initial starting instruction and to load BSP to MS in short time so as to speed up restarting. CONSTITUTION:BFM 4 preserving BSP and MS 12 storing BSP are provided. When power is supplied, BSP is fetched from an external storage device 9, is loaded on MS 12 and is preserved in BFM 4. BSP on MS 12 executes IPL and it is set in an operation state. When it is in the operation state, BSP is fetched from BFM 4 at the time of receiving the initial starting instruction and BSP is loaded on MS 12. Then, BSP on MS 12 concerned executes IPL again.

4. 发明专利

JPH0368587B2 失效
公开(公告)号：JPH0368587B2
公开(公告)日：1991-10-29
申请号：JP15980285
申请日：1985-07-19
申请人： FUJITSU LTD
发明人： HIWATARI AKITO , KISHI MASAHIRO , NOMOTO KAORU
IPC分类号： H04L25/40 , H04L7/04 , H04L13/00 , H04L29/00 , H04L29/04 , H04L29/08 , H04L29/10

5. 发明专利

JPH01102655A SYSTEM FOR TRACING CYCLE STEAL 失效
公开(公告)号：JPH01102655A
公开(公告)日：1989-04-20
申请号：JP26058087
申请日：1987-10-15
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO
IPC分类号： G06F13/28 , G06F11/28 , G06F13/00
摘要： PURPOSE:To perform the trace of a cycle steal without using any hardware of a large scale exclusive for trace control of the cycle steal by making use of the branch tracing function of a CPU of a data processor. CONSTITUTION:A cycle steal control means 4 controls a branch tracing control means 2 at the tracing of a cycle steal to control the cycle steal tracing action of a cycle steal tracing means 3. In such a way, the trace control of the cycle steal is carried out with the use of the branch tracing function of a CPU of a data processor. As a result, a cycle steal tracing action is carried out without using any hardware of a large scale exclusive for trace control of the cycle steal.

6. 发明专利

JPS60254355A CROSS CALL CONTROL SYSTEM 失效
公开(公告)号：JPS60254355A
公开(公告)日：1985-12-16
申请号：JP11140084
申请日：1984-05-31
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , BABA YASUO , KISHI MASAHIRO
IPC分类号： G06F13/12 , H04L29/02
摘要： PURPOSE:To attain the cross call control of I/O control devices by connecting the I/O control devices through two multiplexer channels and two independent communication routes and using plural subchannels defined in respective communication routes. CONSTITUTION:If the switch state of an IFS control circuit 29 is set to neutral, it is checked that a bit in a TAGO.A register 23 which indicates the state of an output pipe line A is ON and a starting address in a BUSO.A register 26 is checked. When the starting address is included within a defined subchannel range, the IFS control circuit 29 is set to the A side, an ISA bit indicating the starting sequence of a TPSR33 is turned on and a microprocessor 18 is interrupted. The microprocessor 18 is started by a program to send information to a control program in a communication control device and store the data written in the BUSO.A register 26 in a local storage part 11.

7. 发明专利

JPS6149264A Priority selecting system 失效
标题翻译：优先选择系统
公开(公告)号：JPS6149264A
公开(公告)日：1986-03-11
申请号：JP17131684
申请日：1984-08-17
申请人： Fujitsu Ltd
发明人： HANAZAWA AKIO , NAKAMURA TAKASHI , KISHI MASAHIRO
IPC分类号： G06F13/362 , G06F13/26
CPC分类号： G06F13/26
摘要： PURPOSE:To prevent to make a priority selected control circuit complicated and to shorten operation time until most preferred adaptor is determined by controlling priority selection with a central control part singly and always grasping an interruption request preserving condition of the adaptor. CONSTITUTION:A communication control processing device CCP is composed of a central control part CC and plural adaptors 10-1n and 20-2n connected through a system bus SB. A priority selecting circuit PS is installed at the central control part CC, and the circuit PS and the adaptors 10-1n of the same interruption level which needs priority processing are linked with a loop PSL for priority selection and priority processing is executed.
摘要翻译：目的：为了防止优先选择控制电路复杂化，缩短操作时间，直到通过中央控制部分单独控制优先级选择来确定最佳适配器，并始终掌握适配器的中断请求保存条件。构成：通信控制处理装置CCP由中央控制部CC和通过系统总线SB连接的多个适配器10-1n，20-2n构成。优先选择电路PS安装在中央控制部分CC处，并且需要优先处理的相同中断级别的电路PS和适配器10-1n与用于优先级选择的循环PSL相关联，并执行优先处理。

8. 发明专利

JPS617964A Data transferring system 失效
标题翻译：数据传输系统
公开(公告)号：JPS617964A
公开(公告)日：1986-01-14
申请号：JP12862384
申请日：1984-06-22
申请人： Fujitsu Ltd
发明人： KISHI MASAHIRO , HANAZAWA AKIO , BABA YASUO
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： PURPOSE:To always execute an optimum data transfer between a channel interface control part and a connection channel device by providing a discriminating means and a means for determining a data transferring system, in order to transfer a data between both of them. CONSTITUTION:In case a connection channel device is a byte multiplexer channel (MXC), when an address-in bit (ADR-I) signal from a channel adaptor is received, a select-out (SEL-O) bit in a TAG.O register 17 is set to ''0''. On the other hand, in case said device is a connection channel block multiplexer channel (BMC) and a selector channel (SLC), even if the ADR-I signal is received, the SEL-O bit holds a ''1'' state, Accordingly, a microprocessor MPU11 discriminates that when the SEL-O bit of the register 17 is ''0'', the connection channel is the MXC, and when it is ''1'', the connection channel is the BMC or the SLC. Subsequently, a kind of the discriminated connection channel device is stored in a local storage part 21.
摘要翻译：目的：为了在通道接口控制部分和连接通道设备之间始终执行最佳数据传输，通过提供鉴别装置和用于确定数据传送系统的装置，以便在两者之间传送数据。构成：如果连接通道器件是字节多路复用器通道（MXC），当接收到来自通道适配器的地址输入位（ADR-I）信号时，TAG中的选择输出（SEL-O）位。 O寄存器17设置为“0”。另一方面，在所述设备是连接信道块复用器信道（BMC）和选择信道（SLC）的情况下，即使接收到ADR-I信号，SEL-O位保持“1”状态因此，微处理器MPU11识别当寄存器17的SEL-O位为“0”时，连接通道为MXC，当为“1”时，连接通道为BMC或 SLC。随后，将一种被鉴别的连接信道设备存储在本地存储部分21中。

9. 发明专利

JPH0448345A DATA PROCESSOR 失效
公开(公告)号：JPH0448345A
公开(公告)日：1992-02-18
申请号：JP15767090
申请日：1990-06-18
申请人： FUJITSU LTD
发明人： KISHI MASAHIRO
IPC分类号： G06F11/16 , G06F11/28
摘要： PURPOSE:To correct a control program without discontinuing the operation of a data processor by writing the corrected control program into a 2nd main storage and opening and closing alternately the 1st and 2nd paths in order to perform a normal operation of the processor based on the corrected control program. CONSTITUTION:The correction is needed for the firmware contents while the firmware contents are alternately read out of the memories 21 and 22 and executed by a microprocessor 24. In such a case, a monitoring part 14 supplies a signal to a memory control circuit 23 via an SVP interface control part 25 to instruct the separation of the memory 21. The circuit 23 actuates a switch circuit in accordance with the received signal and closes and opens the paths set among the memories 21 and 22 and the microprocessor 24 respectively. Thus only the firmware of the memory 22 is carried out by the microprocessor 24. As a result,a control program is corrected without interrupting the operation of a data processor.

10. 发明专利

JPH0361390B2 失效
公开(公告)号：JPH0361390B2
公开(公告)日：1991-09-19
申请号：JP8682085
申请日：1985-04-23
申请人： FUJITSU LTD
发明人： OKADA TATSUO , HIWATARI AKITO , KISHI MASAHIRO
IPC分类号： H04L29/08 , H04L13/00 , H04L29/10

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