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    • 3. 发明专利
    • NEGOTIATION EQUIPMENT
    • JPH09205409A
    • 1997-08-05
    • JP1314296
    • 1996-01-29
    • FUJITSU LTD
    • KUROSAWA KAZUMASAKAI NAOTAKAKANEKO KENICHIMATSUI YUJIUCHIYAMA TSUTOMU
    • H04J3/08H04J3/12
    • PROBLEM TO BE SOLVED: To allow an equipment to flexibly cope with an actual negotiation form by separating incoming/outgoing channels assigned as negotiation lines for each transmission block, coding a speech form and a destination and discriminating a reception signal so as to decode the signal or to relay it. SOLUTION: A transmission line interface means 11 separates incoming/outgoing channels assigned as negotiation lines for each transmission block. A reception relay means 15 separates and discriminates a code, a form and a destination received from the incoming channel and when the inputted signal is addressed to its own station, the means 15 allows the received signal to be decoded and a terminal equipment processing means 13 to give a signal to allow the means 13 to provide the output of a speech signal. When the received signal is not addressed to its own station, the means 15 relays the signal to the outgoing channel for a succeeding transmission block via a transmission means 16. A man-machine interface means 12 sets a speech form and a destination, allows a coding means 14 to multiplex own station information onto a code obtained by compressing a speech signal of its own station terminal with a coding means 14 and allows the resulting multiplexed signal to be sent to the outgoing channel. Thus, a specific field assigned under an existing frame configuration is used to conduct required relay processing and the speech processing of its own station.
    • 4. 发明专利
    • ORDER WIRE LINE
    • JPH0955798A
    • 1997-02-25
    • JP20950895
    • 1995-08-17
    • FUJITSU LTD
    • KANEKO KENICHIUCHIYAMA TSUTOMUKUROSAWA KAZUMASAKAI NAOTAKAMATSUI YUJI
    • H04M3/32H04B3/46H04M3/00
    • PROBLEM TO BE SOLVED: To confirm communication normalcy of the order wire line without spending much labor and long time. SOLUTION: A communication line 3 which forms a two-way communication path is provided between a master station 10 and a slave station 20; and the master station is provided with a 1st signal transmitting means 101 which generates a signal for a specific test and transfers it to the slave station through the communication line and the slave station is provided with a 1st signal sending-back means 201 which receives the signal transferred from the master station, inspects if the signal matches the test, and sends the received signal back to the master station through the communication line when matching is detected. Then the master station is provided with a 1st signal detecting means 102 which receives the signal transferred from the slave station, inspects whether it matches the signal for the test transferred by the 1st signal sending means, and decides that normal communication can be made between the master station 10 and slave station 20 through the communication line 3 when detecting both signals matching each other.
    • 5. 发明专利
    • Channel address conversion system
    • 通道地址转换系统
    • JPS61114352A
    • 1986-06-02
    • JP23472984
    • 1984-11-07
    • Fujitsu Ltd
    • MIYAJIMA SHIGERUKANEKO KENICHIAKASAKA TSUTOMU
    • G06F12/10G06F13/12
    • PURPOSE: To cope with high-speed transfer of data on an I/O and also to avoid the generation of an overrun, etc., by performing the address conversion of high speed equivalent to a TLB (translation look-aside buffer) at the channel side and therefore increasing the number of channels.
      CONSTITUTION: A channel data processor CDP is provided between a main memory MM and a channel CH. The memory MM contains a logical/real address conversion table TB, and the CDP contains a conversion mechanism TM corresponding to a TLB. Four conversion registers are provided to each channel of the mechanism TM to store the result of conversion between a logical address and a real address. A subchannel memory SCM contains a storage area SR for result of conversion. Thus the results of logical/real address conversions of the mechanism TM are stored to the area SR for each subchannel.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:为了应对I / O上的高速数据传输,并且通过执行相当于TLB(转换后备缓冲器)的高速地址转换来避免产生超限等 通道侧,因此增加通道数。 构成:在主存储器MM和通道CH之间提供通道数据处理器CDP。 存储器MM包含逻辑/真实地址转换表TB,并且CDP包含对应于TLB的转换机制TM。 四个转换寄存器被提供给机构TM的每个通道以存储逻辑地址和实际地址之间的转换结果。 子通道存储器SCM包含用于转换结果的存储区域SR。 因此,机制TM的逻辑/实际地址转换的结果被存储到每个子信道的区域SR。