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1. 发明专利

JPH1079963A FAILSAFE CIRCUIT IN INTER-TRANSMISSION DEVICE 失效
公开(公告)号：JPH1079963A
公开(公告)日：1998-03-24
申请号：JP23347196
申请日：1996-09-03
申请人： FUJITSU LTD
发明人： KIMURA TERUO , HORIE TATSUYA
IPC分类号： H04B3/46 , H04B17/00 , H04Q3/42
摘要： PROBLEM TO BE SOLVED: To provide a failsafe circuit which can prevent one transmission device that becomes an off state by an effect of a signal from an other transmission device when a power source of a transmission device is cut off from performing a malfunction in an inter-transmission device interface. SOLUTION: This circuit has power sources 4 and 6 which are independent of each other, a three-state buffer 40 is provided on the output stage of an interface circuit 12 of one transmission device 1 that performs inputs and outputs of a signal, a voltage output terminal of the source 6 of the other transmission device 2 is connected to an output control terminal of the buffer 40, an 'H' level is supplied to the output control terminal when the source 6 of the device 2 is normal, the buffer 40 becomes a signal transit state, an 'L' level is supplied to the output control terminal when the source 6 of the device 2 is abnormal, and the buffer 40 becomes an off state.

2. 发明专利

JPH0750647A INSETTION PROCESSING CIRCUIT TO INDICATOR H4 失效
公开(公告)号：JPH0750647A
公开(公告)日：1995-02-21
申请号：JP19500793
申请日：1993-08-06
申请人： FUJITSU LTD
发明人： KIMURA TERUO
IPC分类号： H04J3/08
摘要： PURPOSE:To enable the insertion of number of bytes from an H4 to the head of an ATM cell which comes first after the H4 into the H4 by providing an H4 insertion part inputting the output m of a second arithmetic circuit and inserting into the area of the H4 in the timing of the indicator H4 of a pass overhead. CONSTITUTION:A pulse showing the last of each line of a frame format is inputted in a 260XN byte counter 1 and the number of bytes 260XN in the range of a main information area is counted. The output value of the counter 1 is latched by a latch circuit 2 by the timing of the pulse showing the head of an ATM cell which comes next to the overhead of each line and the number of bytes n from the last of the overhead of each line to the head of the ATM cell which comes first is determined. In an arithmetic circuit 3, (48-n)XN=X is determined. In an arithmeic circuit 4, m=53XX is determined and it is inputted in an H4 insertion part 5. In the insertion part 5, the only m just before the timing pulse of the indiator H4 is inputted is inserted in the H4. Therefore, the number of byte up to the head of the ATM cell which comes next to the H4 can be inserted into the H4.

3. 发明专利

JPH04276934A BIT ERROR RATIO MEASUREMENT METHOD AND ITS CIRCUIT 失效
公开(公告)号：JPH04276934A
公开(公告)日：1992-10-02
申请号：JP3859191
申请日：1991-03-05
申请人： FUJITSU LTD
发明人： KIMURA TERUO
IPC分类号： H04B3/46 , H04L1/00 , H04L1/22
摘要： PURPOSE:To measure a bit error ratio caused in a transmission line or the like in a short time with high accuracy with respect to the bit error ratio measurement method and its circuit. CONSTITUTION:A clock counter circuit 2 and a bit error counter circuit 4 start simultaneously counting a clock pulse signal and a bit error pulse signal, and when the count of the clock pulse signal reaches a predetermined value, the count of the bit error pulse signal is divided by the predetermined count by a divider circuit 6 to output a bit error ratio.

4. 发明专利

JPH03228442A PROTECTING CIRCUIT 失效
公开(公告)号：JPH03228442A
公开(公告)日：1991-10-09
申请号：JP2249090
申请日：1990-02-01
申请人： FUJITSU LTD
发明人： IKUMA HIROSHI , KIMURA TERUO
IPC分类号： H04L1/00
摘要： PURPOSE:To reduce the circuit scale by constituting the protecting circuit so that a count value of a counter is set as an alarm signal, and also, a load signal generating circuit is controlled. CONSTITUTION:The protecting circuit is provided with a counter 1 for counting the number of protecting stages and latching an alarm output, a decoder 2 for decoding the number of front and rear protective stage -1, a selector 3 for selecting the number of front or rear protective stages -1, and a load signal generating circuit 4 for generating a load signal of the counter from an alarm signal, an error signal and a selector output. This circuit is constituted so that a count value of the counter 1 is latched as the alarm signal, and also, reduced to the load signal generating circuit 4, and the load signal for the front protection and for the rear protection of the error signal. In such a way, the load signal and the load value of the counter can be controlled so as to show the number of protective stages and the alarm state at present by one counter, and also, setting of the number of protective stages can be selected from the outside.

5. 发明专利

JPS63222520A B8ZS CODER/DECODER CIRCUIT 失效
公开(公告)号：JPS63222520A
公开(公告)日：1988-09-16
申请号：JP5722887
申请日：1987-03-12
申请人： FUJITSU LTD
发明人： FUKUCHI NOBUYUKI , KIMURA TERUO , TAKAHASHI YOSHITOSHI
IPC分类号： H03M5/16 , H03M7/14
摘要： PURPOSE:To miniaturize the circuit scale and low power consumption by constituting a mask pattern forming with a dummy inserted by one stage of R-S flip-flop in detecting 8 consecutive zero pattern. CONSTITUTION:In detecting the 8 consecutive zero pattern, the generating circuit of a dummy pattern inserted to the pattern mask processing for AMi (Alternate mark inversion) processing is formed by a latch section 30 comprising one stage of R-S flip-flop do the like in a way that the 8 consecutive zero applies 3-bit delay to an output '1' of a detection circuit 2. Thus, the miniaturization of the circuit scale and low power consumption are attained.

6. 发明专利

JPH0722927A CLOCK SWITCHING CIRCUIT 失效
公开(公告)号：JPH0722927A
公开(公告)日：1995-01-24
申请号：JP15023793
申请日：1993-06-22
申请人： FUJITSU LTD
发明人： TAKIZAWA YUJI , KAWAI MASAAKI , NAITO HIDETOSHI , TAJIMA KAZUYUKI , IKEDA TOSHIMI , KIMURA TERUO
IPC分类号： H03K5/00 , H03K17/00
摘要： PURPOSE:To eliminate a short periodic clock and to eliminate the malfunctions of various kinds of equipments operating by the clock by outputting the clock in a mask state which is held in an H level state over the period which is longer than a clock half period from a selector at the time of the switching operation of the selector. CONSTITUTION:When a mask command signal MSK becomes an H level, the input data of a data input terminal D or a mask command signal MASK is made to be outputted, and the mask control signals M1 and M2 from data and an output terminal Q are made to rise and are made an H level state by the rise timing of the first clocks CLK 1 and CLK 2 after the mask command signal MASK becomes the H level state by D flip flops 17A and 17B, in a control circuit 15. Thus, OR gates 10A and 10B are made a mask operation states and the clock outputs CLK 1M and CLK 2M from these are held in the H level. Namely, the switching completion signal EXCHG of an AND gate 18 is made to rise and a control signal S is made to be outputted from a D flip flop 16 to a selector 3.

7. 发明专利

JPS6423620A DUTY FACTOR CORRECTING CIRCUIT 失效
公开(公告)号：JPS6423620A
公开(公告)日：1989-01-26
申请号：JP17950487
申请日：1987-07-17
申请人： FUJITSU LTD
发明人： KIMURA TERUO
IPC分类号： H03K23/64 , H03K21/02
摘要： PURPOSE:To automatically correct a duty factor to about 50%, by outputting an odd dividing output signal outputted from an odd dividing means after the output signal is re-tapped by means of an output means by using the output signal of a shifting means produced by optionally selecting the shifting quantity of the shifting means. CONSTITUTION:The titled circuit is provided with an odd dividing means 10 which produces an odd dividing output signal at the timing of one of two clocks CLK1 and CLK2 having phases opposite to each other, shifting means 20 which shifts the cycle of the other of the two clocks CLK1 and CLK2 by a plural bits quantity, output means 30 which corrects the duty factor of an odd dividing output signal which is produced by synthesizing the odd dividing output signal outputted from the means 10 and the signal of the shifting means 20 to about 50%, and selector means 40 which selects and controls the shifting quantity to be shift-processed by the shifting means 20. The AND of the output signal of the odd dividing means 10 and the output of the shifting means 20 is taken and the output signal of the means 10 is re-tapped. Therefore, the output signal of the odd dividing circuit 20, whose duty factor is corrected to about 50%, is obtained.

8. 发明专利

JPS6195649A Mark rate detection circuit 失效
标题翻译：标记检测电路
公开(公告)号：JPS6195649A
公开(公告)日：1986-05-14
申请号：JP21641984
申请日：1984-10-17
申请人： Fujitsu Ltd
发明人： OTSUKA MASANORI , KIMURA TERUO
IPC分类号： H04L25/02 , H03M13/51 , H04L1/20 , H04L25/49
CPC分类号： H04L1/20
摘要： PURPOSE:To speed up the detection of a mark rate by providing an n-rotation counter counting serial input data and a decoder decoding the count output and outputting a mark rate detection signal at each n bits of the input data. CONSTITUTION:Serial input data (a) is converted into an RZ signal (c) by a converting circuit 1 according to a clock signal (b) and fed to a clock terminal CK of a counter 2. Further, the clock signal (b) is subjected to 1/n frequency- division by a frequency division circuit 5 and fed to a reset pulse generating circuit 4 and a latch circuit 7. A reset pulse is generated at each n-set clock signal from the reset pulse generating circuit 4 to reset the counter 2. An output signal of the counter 2 and a flip-flop 3 is fed to a decoder 6, the output signal of which is latched by a frequency division output signal of the frequency division circuit 5 at the latch circuit 7 and its latch output signal is a mark rate detection signal.
摘要翻译：目的：通过提供对计数串行输入数据的n旋转计数器和解码计数输出的解码器，并在输入数据的每n位输出标记速率检测信号，加快检测标记率。构成：根据时钟信号（b），转换电路1将串行输入数据（a）转换成RZ信号（c），并馈送到计数器2的时钟端子CK。此外，时钟信号（b）通过分频电路5进行1 / n分频，并馈送到复位脉冲发生电路4和锁存电路7.在复位脉冲发生电路4的每个n组时钟信号上产生复位脉冲，复位计数器2.计数器2和触发器3的输出信号被馈送到解码器6，解码器6的输出信号由锁存电路7处的分频电路5的分频输出信号锁存，其锁存输出信号是标记速率检测信号。

9. 发明专利

JPH0630085A COMMUNICATION EQUIPMENT WITH INSERTION FUNCTION OF ERROR CODE 失效
公开(公告)号：JPH0630085A
公开(公告)日：1994-02-04
申请号：JP18017092
申请日：1992-07-08
申请人： FUJITSU LTD
发明人： KIMURA TERUO , SUZUKI TERUHIKO
IPC分类号： H04J3/12 , H04J3/14 , H04L7/00 , H04L29/14
摘要： PURPOSE:To perform the test of a monitoring function profitably by inserting an error code to a signal relating to the monitoring function out of communication signals via a monitor signal insertion circuit. CONSTITUTION:Communication is performed by stopping an error insertion control circuit 4 from the outside and sending a normal signal without inserting an error to a monitor signal. Meanwhile, a delivery test or periodical inspection is performed by driving the error control circuit 4 from the outside, and sending it by inserting the error to the monitor signal via the monitor signal insertion circuit 3. Receivers 6-9 operate the monitoring function by the monitor signal to which the error is inserted. For example, when the monitoring function is a synchronous monitoring function, the error is inserted to a synchronizing signal, therefore, no synchronous detection is performed when the synchronous monitoring function is operated normally, and a synchronous alarm is issued after a prescribed operation is performed. Also, in an error correction circuit, a signal outputted by performing a corrective operation is compared with a signal before the error is inserted. In such a manner, it is possible to test the normal/abnormal state of the monitoring function.

10. 发明专利

JPH04281643A ATM CELL MULTIPLEXER 失效
公开(公告)号：JPH04281643A
公开(公告)日：1992-10-07
申请号：JP4523891
申请日：1991-03-11
申请人： FUJITSU LTD
发明人： KIMURA TERUO
摘要： PURPOSE:To improve the work efficiency at a low cost for the test measurement for a protect time or the like in a receiver with respect to the ATM cell multiplexer. CONSTITUTION:The multiplexer is provided with a CRC arithmetic means 20 receiving an ATM cell in which an arithmetic result part of a header is set idle and obtaining a CRC arithmetic error causing an error for the CRC arithmetic operation intentionally and a CRC arithmetic normal value and with an adder means 21 adding the CRC arithmetic error to the arithmetic result part or the CRC arithmetic normal value to the arithmetic result part.

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