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1. 发明专利

JPWO2011070810A1 選択装置有权
公开(公告)号：JPWO2011070810A1
公开(公告)日：2013-04-22
申请号：JP2011510759
申请日：2010-05-31
申请人：株式会社 Trigence Semiconductor , 株式会社 Trigence Semiconductor
发明人：彰安田 , 彰安田 , 淳一岡村 , 淳一岡村
IPC分类号： H03M1/74 , H03M1/10 , H03M5/16
CPC分类号： H03M1/066 , H03M1/74 , H03M3/502 , H04R3/00 , H04R2420/03
摘要：デジタル選択信号を取得する取得部と、0値の出力を命令されることが可能な複数の単位セルそれぞれに選択信号を出力する出力部とを有し、前記選択信号は前記単位セルに前記選択信号に対応する値の出力を命令し、前記複数の単位セルに出力される選択信号が命令する出力の値の合計は前記デジタル選択信号に対応して決まる値であり、前記デジタル選択信号に対応する出力が0値であれば、0でないN値の出力を命令する選択信号が出力される単位セルが存在することを特徴とする選択装置を提供する。

4. 发明专利

JPH11112331A TERNARY SIGNAL DEVICE AND METHOD THEREFOR 失效
公开(公告)号：JPH11112331A
公开(公告)日：1999-04-23
申请号：JP14074898
申请日：1998-05-22
申请人： SUN MICROSYSTEMS INC
发明人： GARNETT PAUL JEFFREY
IPC分类号： H03K19/20 , H03M5/16 , H04L25/49
摘要： PROBLEM TO BE SOLVED: To provide improvement for providing many options or extended ternary encoding by performing the extended ternary decoding of a ternary input signal in response to the output signal from a window comparator output in both phases. SOLUTION: When a pin 12 has a low value L, the outputs B and A of 1st and 2nd comparators 16 and 18 have low values L, which are encoded by an encoder 24, so that an output X has a high value H and outputs Y and Z have low values L. Similarly, when the pin 12 has an intermediate value M, the outputs B and A have low and high values L and H, which are encoded by the encoder 24, so that the output Y has a high value H and the outputs X and Z have low values L. When the pin 12 has a high value H, on the other hand, the outputs B and A have high values H, which are encoded, so that the output Z has a high value H and the outputs X and Y have low values L. When the pin is open, resistances R1 and R2, and R3 to R5 for forcibly setting the pin to an intermediate value M are set equally to supply a reference voltage to the comparators 16 and 18.

6. 发明专利

JPH09294076A HONOPOLAR-BIPOLAR CODE CONVERSION CIRCUIT 失效
公开(公告)号：JPH09294076A
公开(公告)日：1997-11-11
申请号：JP10520496
申请日：1996-04-25
申请人： MIYAGI NIPPON DENKI KK , NIPPON ELECTRIC ENG , NEC CORP
发明人： YANAGISAWA HIROKI , KIMURA MADOKA , YAMANAKA HIDEAKI
IPC分类号： H03K5/00 , H03M5/04 , H03M5/16 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To correct a duty ratio by increasing an identification level when a pulse signal with a high level and whose duty ratio is deteriorated is received. SOLUTION: An inverted output of a differential amplifier 1 is fed back to a noninverting input via a feedback resistor 6, while the noninverting output is fed back to an inverting input via a peak level detection circuit 2, a voltage correction circuit 3 and a feedback resistor 7. The voltage correction circuit 3 corrects an output voltage from the peak level detection circuit 2 when the output voltage is a reference voltage while providing extension of its change increasingly and feeds back the corrected signal to the inverting input. Thus. the identification level is higher when the level of the input signal is the reference voltage level or over to correct the input signal whose duty ratio is extended in a decreasing direction.

8. 发明专利

JPH088752A BIPOLAR CLOCK DISTURBANCE DETECTION CIRCUIT 失效
公开(公告)号：JPH088752A
公开(公告)日：1996-01-12
申请号：JP13276494
申请日：1994-06-15
申请人： NEC CORP
发明人： TAKAHASHI YASUNORI
IPC分类号： G06F1/04 , H03K5/19 , H03M5/16
摘要： PURPOSE:To make it possible to detect the abnormality of any bipolar clock by deciding that the bipolar clock is abnormal when the generation timing of detected violation is not matched with a prescribed timing pattern. CONSTITUTION:The outputs of positive and negative polarity pulse detection circuits 11 and 12 are inputted in a violation detection circuit 15 via a logical OR circuit 14. The circuit 15 detects the violation between the output signals SPLUS and SMINUS of the circuits 11 and 12 by defining a signal SCLOCK as a clock. When the output signal SOUT of the circuit 15 is inputted in a counter 16, a count-up is performed by synchronizing with the signal SCLOCK and the circuit 15 outputs the signal according to violation locations, a count value is reset. When an alarm detection circuit 17 monitors the count value of the counter 16 and the counter 16 is reset by a value which is different from that at a normal time, an alarm showing an abnormality is outputted when the reset is not performed in the timing that the violation should be generated.

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