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1. 发明专利

JP2538786B2 失效
公开(公告)号：JP2538786B2
公开(公告)日：1996-10-02
申请号：JP30792087
申请日：1987-12-04
申请人： FUJITSU LTD
发明人： SUDA ATSUSHI , SUZUKI TERUHIKO , ITO ATSUSHI
IPC分类号： H03K21/38 , H03K23/00 , H03K23/50

2. 发明专利

JPH03235421A CLOCK REGENERATION CIRCUIT 失效
公开(公告)号：JPH03235421A
公开(公告)日：1991-10-21
申请号：JP3121090
申请日：1990-02-09
申请人： FUJITSU LTD
发明人： SAITO YOSHIHIRO , SUZUKI TERUHIKO
IPC分类号： H03L7/085
摘要： PURPOSE:To offer a clock regeneration circuit which has few phase errors and has a wide lock range through simple configuration by using a D type flip flop as a phase comparator to compare the phases of input data and a regenerative clock with each other. CONSTITUTION:When the phases of the input data 1 and the regenerative clock 2 coincide with each other, the output of the D type flip flop 11 varies into '1', '0' like 3. As the result, the output 4 of a low pass filter 12 becomes some DC potential, and a loop is stabilized. On the contrary, when the phase of the regenerative clock is delayed later than the input data, since the regenerative clock 2 becomes '1' always at the time of the rise-up of the data 1, the Q output of the D type flip flop 11 becomes '1' always. As the result, the output level 4 of the low pass filter 12 rises up gradually, and the output frequency of a VCO 13 becomes higher gradually, and the phase trends toward a direction in which it advances, and a system is stabilized.

3. 发明专利

JPH03177112A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH03177112A
公开(公告)日：1991-08-01
申请号：JP31710589
申请日：1989-12-05
申请人： FUJITSU LTD
发明人： SAITO YOSHIHIRO , SUZUKI TERUHIKO
IPC分类号： H03L7/087 , H04L7/033
摘要： PURPOSE:To prevent erroneous synchronization between receive data and a receiving clock by executing frequency comparison between the reception clock and a transmission clock, and when a compared result is more than a prescribed value, interrupting the operation of a phase comparator, and in addition, driving a low pass filter, an amplifier and a voltage controlled oscillator, and controlling the compared result so that it is within the prescribed value. CONSTITUTION:The frequencies of the reception clock B and the transmission clock C are compared with each other by a frequency comparator 5, and when the compared result is more than the prescribed value, a phase locked loop circuit (PLL circuit) is driven, and the frequencies of the reception clock B and the transmission clock C are controlled so as to becomes close to each other. Besides, when the compared result is below the prescribed value, a non- operating state is generated to stop the drive to the PLL circuit. Thus, when the compared result is other than the prescribed value, the reception clock and the transmission clock can be restored to a synchronous state, and the errorneous synchronization at different frequencies can be prevented.

4. 发明专利

JPH021412B2 失效
公开(公告)号：JPH021412B2
公开(公告)日：1990-01-11
申请号：JP9836681
申请日：1981-06-26
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO , OGAWA TADAO , ARAI MASANORI , NISHIZAKI KOJI , ENDO TAKEMI
IPC分类号： H03M5/04 , H03K5/00 , H03K17/66 , H03K19/20 , H03M5/18 , H04L25/02 , H04L25/22 , H04L25/49

5. 发明专利

JPS6248412B2 失效
公开(公告)号：JPS6248412B2
公开(公告)日：1987-10-14
申请号：JP21011682
申请日：1982-11-30
申请人： FUJITSU LTD
发明人： ARAI MASANORI , NISHIZAKI KOJI , SUZUKI TERUHIKO
IPC分类号： H03K5/19 , H04B1/74 , H04B17/00 , H04B17/18 , H04B17/29 , H04L1/22 , H04L25/02

6. 发明专利

JPS62175011A N-MULTIPLYING CIRCUIT 失效
公开(公告)号：JPS62175011A
公开(公告)日：1987-07-31
申请号：JP6292686
申请日：1986-03-20
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H03K5/00
摘要： PURPOSE:To miniaturize the circuit with a large-scaled integration by forming N pieces of the pulse train, in which the phase is different only by T, from an input pulse train and obtaining the pulse train to add these and execute the N-multiplication. CONSTITUTION:The circuit is composed of the first converting circuit 4-1 in which an input pulse train is inputted, either of the rise or the fall of an input pulse is used, the period is the same as the period of the input pulse and the pulse width is converted to an I/N pulse column, the K-th converting circuits 4-2...4-N in which the phase is converted to the pulse train to shift only (K-1) IN of the period by the same pulse train as the output of the first converting circuit to all integers K from 2 to N and an adding circuit 5 to add the output of the first - N converting circuits. At respective converting circuits, either of the rise or the fall of the input pulse train is used and the pulse of the prescribed pulse width and the phase is generated. Thus, an N-multiplying signal obtained by adding respective pulses is not influenced by the pulse width of the input pulse and since a tuning circuit is not necessary, LSI is easily executed.

7. 发明专利

JPS6218137A LIGHT RECEPTION EQUIPMENT 失效
公开(公告)号：JPS6218137A
公开(公告)日：1987-01-27
申请号：JP15602585
申请日：1985-07-17
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H04B10/60 , H04B10/00 , H04B10/40 , H04B10/50 , H04B10/69
摘要： PURPOSE:To lower the minimum photodetection level, to widen the frequency band and to widen sufficiently the dynamic range by providing a transformer impedance type optical reception circuit having a large feedback resistor to the pre-stage and supplying the output to a HPF. CONSTITUTION:A photoelectric conversion circuit 1, an amplifier 2 and a feedback resistor Rf1 constitute a transformer impedance type photo reception circuit constituting the pre-stage of a photo receiver. The resistance of the resistor Rf1 is selected to be a sufficiently larger value than the feedback resistance of a conventional circuit. The post-stage of the photo receiver is a frequency characteristic compensating HPF comprising a capacitor C1 and a resistor R1. Through the above constitution, the minimum photodetection level is lowered by increasing the resistor Rf1 and high sensitivity is attained. On the other hand, the required frequency characteristic is obtained by cancelling the transformer impedance at low frequencies by the filter comprising C1, R1. Although the frequency band is apt to go to narrow, it is prevented by setting the resistor Rf1 properly.

8. 发明专利

JPS6199431A Laser diode driving device 失效
标题翻译：激光二极管驱动器件
公开(公告)号：JPS6199431A
公开(公告)日：1986-05-17
申请号：JP21937284
申请日：1984-10-20
申请人： Fujitsu Ltd
发明人： SUZUKI TERUHIKO
IPC分类号： H04B10/556 , H04B10/00 , H04B10/07 , H04B10/524
CPC分类号： H04B10/508 , H04B10/504
摘要： PURPOSE:To reduce the occurrence of erroneous information discrimination in optical communication to improve the quality of communication by generating an optical output having the same pulse rise waveform independently of a bit preceding current pulse application of a current bit. CONSTITUTION:One pulse waveform generating circuit 31 receives the clock signal from a clock signal generator 2 and outputs a pulse waveform sequence of 50% duty. The other pulse waveform generating circuit 32 receives the clock signal from the clock signal generator 2 and outputs a pulse waveform sequence of 60% duty. The output of a switching circuit 4 is applied to one input terminal of an AND gate 6, and the output of the AND logic between this output and transmission NRZ data applied to the other input terminal of the AND gate 6 is applied to the gate of a laser diode driving transistor 7 to turn on or off the current flowed to a laser diode 8. Thus, a laser diode driving current waveform having the same pulse rise timing is obtained independently of data of the preceding bit.
摘要翻译：目的：为了减少光通信中错误信息识别的发生，通过产生具有与当前位的当前脉冲施加之前的位相同的脉冲上升波形的光输出来提高通信质量。构成：一个脉冲波形发生电路31从时钟信号发生器2接收时钟信号，并输出占空比为50％的脉冲波形序列。另一个脉冲波形发生电路32从时钟信号发生器2接收时钟信号，并输出占空比为60％的脉冲波形序列。开关电路4的输出被施加到与门6的一个输入端，并且施加到与门6的另一个输入端的该输出和发送NRZ数据之间的与逻辑的输出被施加到激光二极管驱动晶体管7导通或关断流向激光二极管8的电流。因此，独立于前一位的数据获得具有相同脉冲上升时间的激光二极管驱动电流波形。

9. 发明专利

JPS60180314A DELAY CIRCUIT 失效
公开(公告)号：JPS60180314A
公开(公告)日：1985-09-14
申请号：JP3679784
申请日：1984-02-28
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO , ARAI MASANORI , OKADA KIMIYOSHI , TSUDA TAKASHI
IPC分类号： H03H11/26 , H03H7/09 , H03H7/32 , H03K5/13
摘要： PURPOSE:To miniaturize the circuit and to set easily the delay time by providing a full band transmission filter comprising inductances connected in series and a capacitor connected in parallel with the midpoint of the inductances between stages of inverting gates consisting of an emitter coupling logical circuit giving a prescribed time of delay to a signal string between the inverting gate stages. CONSTITUTION:The full band transmission filter 11 is provided in place of a coaxial cable and sets an optional delay time of nearly ns (nano sec) to high- speed data inverted by the emitter coupling logical (EOL) circuit. The capacitor 22 is connected in parallel with the midpoint of the inductances L211, L212 connected in series and grounded in the full band transmission filter 11. The filter 11 is characterized in that the amplitude is transmitted as it is over the entire frequency range and only the phase is shifted, allowing to set a prescribed delay time. A desired delay time is obtained by providing the full band transmission filter to the inter-stage of the ECL circuit and setting optionally the constant and it is easy to change the delay time. Since the filter is formed by combining high frequency LC, the circuit is miniaturized.

10. 发明专利

JPS60103744A RECEIVING CIRCUIT 失效
公开(公告)号：JPS60103744A
公开(公告)日：1985-06-08
申请号：JP21123483
申请日：1983-11-10
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H04B10/60 , H04B10/00 , H04B10/40 , H04B10/50 , H04B10/66
摘要： PURPOSE:To expand the frequency band of a trans impedance without increasing thermal noise by inserting parallel resonance circuit higher than a cut-off frequency in series with a feedback resistor. CONSTITUTION:The parallel circuit having a resonance frequency higher than the cut-off frequency, i.e., an inductance L, a capacitor C2 and a damping resistor R are inserted in series with a feedback resistor Rf of an amplifier 2. The trans impednace frequency band of a trans impedance type receiving circuit 3' is extended in this case. Since the value of the resistor Rf is not changed and the resistor R is connected in series with the resistor Rf, thermal noise is reduced.

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