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1. 发明专利

JPH10123172A METHOD AND DEVICE FOR CALIBRATING PHYSICAL QUANTITY SENSOR 失效
公开(公告)号：JPH10123172A
公开(公告)日：1998-05-15
申请号：JP27777496
申请日：1996-10-21
申请人： FUJI ELECTRIC CO LTD , FUJITSU TEN LTD
发明人： KAMIYANAGI KATSUMICHI , NISHIKAWA MUTSUO , NAKAZAWA HARUO , FUNO HIDEKAZU
IPC分类号： G01P21/00 , G01L27/00
摘要： PROBLEM TO BE SOLVED: To calibrate a physical quantity sensor, especially one regarding force easily. SOLUTION: When a small physical quantity sensor is calibrated, an additional mass 300 whose mass (m) is confirmed in advance is placed on a thick- walled part 103, thus enabling the thin-walled part to be deformed as if an acceleration or a pressure is generated and a physical quantity sensor to detect a physical quantity such as acceleration and pressure being equivalent to the mass (m) of the additional mass 300. An output for the mass (m) and the expression of a calibration straight line when an intrinsic physical quantity is applied are obtained in advance. A sensitivity equivalent to the sensor in the intrinsic physical quantity can be obtained from the output by the addition mass 300 using the calibration straight line expression. The sensitivity equivalent to the sensor in the intrinsic physical quantity due to the calibration straight line can be automatically calculated by a calibration device.

2. 发明专利

JP2019021689A 半導体装置の製造方法审中-公开
公开(公告)号：JP2019021689A
公开(公告)日：2019-02-07
申请号：JP2017136611
申请日：2017-07-12
申请人： FUJI ELECTRIC CO LTD
发明人： IGUCHI KENICHI , NAKAZAWA HARUO
IPC分类号： H01L21/223 , H01L21/22 , H01L21/225 , H01L21/268 , H01L21/28 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/417 , H01L29/47 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/868 , H01L29/872
摘要：【課題】表面側から深い位置までp型不純物が高濃度に導入された不純物導入層を備えた半導体装置を効率よく製造できる半導体装置の製造方法を提供する。【解決手段】半導体装置の製造方法は、n型の半導体である被導入層2の表面上に、アルミニウム及びベリリウムを一体的に含有する不純物源膜4を形成する工程と、第1のレーザー光を不純物源膜4に向けて照射することにより、被導入層2の内部に前記アルミニウム及び前記ベリリウムを同時に導入してp型の不純物導入層を形成する工程と、を含む。【選択図】図4

3. 发明专利

JP2014220516A 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014220516A
公开(公告)日：2014-11-20
申请号：JP2014144585
申请日：2014-07-14
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： NEMOTO MICHIO , KIRISAWA MITSUAKI , NAKAZAWA HARUO
IPC分类号： H01L29/861 , H01L21/265 , H01L21/268 , H01L21/322 , H01L21/329 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/868
CPC分类号： H01L21/26 , H01L21/32 , H01L29/78
摘要：【課題】半導体基板の裏面研削工程を含む製造方法において、ソフトリカバリー特性を有する素子を有する半導体装置を提供すること。【解決手段】N型半導体基板1の一方の主面にPアノード層2とアノード電極3を形成した後、電子線を照射して半導体基板1の中に結晶欠陥を導入する。次いで、半導体基板1の他方の主面を研削して薄板化し、研削により露出した面から半導体基板1にリンをイオン注入する。次いで、その注入面にダブルパルス法でYAGレーザを照射し、半導体基板1の中に注入されたリンを電気的に活性化させるとともに、レーザ光の照射面から、薄板化されたウェハー全体の厚さの5〜30%に相当する深さまでの領域の結晶欠陥を回復させて、ソフトリカバリーとする。【選択図】図4
摘要翻译：要解决的问题：提供一种半导体器件，其包括在包括研磨半导体衬底的背面的步骤的制造方法中具有软恢复特性的元件。解决方案：在P阳极层2和阳极电极3之后形成在N型半导体衬底1的一个主表面上，用电子束照射一个主表面以在半导体衬底1中引入晶体缺陷。半导体衬底1的另一个主表面被研磨和变薄，并且离子从通过研磨暴露的表面对半导体衬底1进行磷光体的注入。通过双重脉冲方法用YAG激光照射注入表面，以激发注入在半导体衬底1中的荧光体，并将激光照射面的区域中的晶体缺陷扩大到对应于激光的照射面的5〜30％的深度恢复整个薄的晶片的厚度，从而实现软恢复。

4. 发明专利

JP2012199577A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012199577A
公开(公告)日：2012-10-18
申请号：JP2012127604
申请日：2012-06-04
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NEMOTO MICHIO , KIRISAWA MITSUAKI , NAKAZAWA HARUO
IPC分类号： H01L29/868 , H01L21/265 , H01L21/322 , H01L21/329 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method including a step of grinding a rear face of a semiconductor substrate by which an element having a soft recovery characteristic can be produced.SOLUTION: A P-anode layer 2 and an anode electrode 3 are formed on one principal surface of an N-type semiconductor substrate 1, and then, the one principal surface is irradiated with an electron beam to introduce crystal defects in the semiconductor substrate 1. Next, the other principal surface of the semiconductor substrate 1 is ground and thinned, and ion implantation of phosphor is performed to the semiconductor substrate 1 from a surface exposed by the grinding. Next, the implantation surface is irradiated with a YAG laser by the double pulse method to activate phosphor implanted in the semiconductor substrate 1 electrically, and the crystal defects in a region from the irradiation surface of laser light to a depth corresponding to 5-30% of a thickness of the whole thinned wafer are recovered, thus the soft recovery is achieved.
摘要翻译：解决的问题：提供一种制造方法，该方法包括研磨可以生产具有软恢复特性的元件的半导体衬底的背面的步骤。解决方案：在N型半导体衬底1的一个主表面上形成P阳极层2和阳极电极3，然后用电子束照射一个主表面，以将晶体缺陷引入到半导体衬底1。接下来，研磨和减薄半导体衬底1的另一个主表面，并从由研磨暴露的表面对半导体衬底1进行磷光体的离子注入。接下来，通过双脉冲方式用YAG激光照射注入表面，以电激活注入到半导体衬底1中的荧光体，并将激光照射表面的区域中的晶体缺陷扩大到对应于5-30％恢复整个薄的晶片的厚度，从而实现软恢复。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JPH04217854A MOVABLE FIELD LINEAR MOTOR 失效
公开(公告)号：JPH04217854A
公开(公告)日：1992-08-07
申请号：JP541291
申请日：1991-01-22
申请人： FUJI ELECTRIC CO LTD
发明人： OSAWA MASAHIRO , SHINGU AKIJI , HIKITA KAZUMI , NAKAZAWA HARUO
IPC分类号： H02K41/02 , H02K41/03 , H02P7/00 , H02P25/06
摘要： PURPOSE:To dissolve problem of spark and noise in conventional brush system by employing brushless power supply control for an armature coil. CONSTITUTION:In a movable field linear motor comprising a combination of a stator having armature coils 3 arranged along the moving path of a rotor 1 and the rotor 1 having a field permanent magnets, 2 opposing to the armature coil 3, each armature coil 3 on the stator side is connected through a reed switch 5 with a feeder line 4. Power supply control is performed such that the reed switch 5 is switched by the magnetic force of the field permanent magnet 2 carried on the rotor 1 according to the movement thereof thus feeding current only to an armature coil 3 opposing to the field permanent magnet 2.

6. 发明专利

JP2014143435A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014143435A
公开(公告)日：2014-08-07
申请号：JP2014075312
申请日：2014-04-01
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NAKAZAWA HARUO , HARADA TAKAHITO , SHIGETA FUMIO , FUKUDA KYOHEI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is able to suppress degradation in semiconductor characteristics, due to stress concentration on a corner part of a recessed part, resulting from solder heat hysteresis, in a semiconductor chip having the recessed part, which is formed from a non-penetration V-shaped groove, in a semiconductor substrate.SOLUTION: The surface of an n-type wafer 1 has a p-type diffusion layer 31 of a grid pattern. The back of the n-type wafer 1 has a grid pattern of the same pitch as the grid pattern on the surface. A V-shaped groove 21b is provided. The V-shaped groove 21b has a bottom face, parallel to the back, from which the p-type diffusion layer 31 is exposed, and tapering side faces 9d extending from the bottom face. The back surrounded by the tapering side faces 9d has a p-type semiconductor layer. A p-type separation layer 4b that conductively connects the p-type diffusion layer 31 of the surface and the p-type semiconductor layer of the back is provided along the side faces 9d. In the V-shaped groove 21b, a portion near the intersection of a corner of each side face and the bottom face has a chamfered face.
摘要翻译：要解决的问题：为了提供能够抑制半导体特性劣化的半导体器件，由于在具有凹部的半导体芯片中由于焊料热滞后而导致的凹部的角部的应力集中，由半导体衬底中的非穿透V形槽形成。解决方案：n型晶片1的表面具有栅格图案的p型扩散层31。 n型晶片1的背面具有与表面上的网格图案相同的间距的网格图案。设置有V形槽21b。 V形槽21b具有平行于背面的底面，p型扩散层31从该背面暴露，并且从底面延伸的锥形侧面9d。被锥形侧面9d包围的背面具有p型半导体层。沿着侧面9d设置导电性地连接表面的p型扩散层31和背面的p型半导体层的p型分离层4b。在V形槽21b中，靠近每个侧面的角部和底面的交点的部分具有倒角面。

7. 发明专利

JP2012089866A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012089866A
公开(公告)日：2012-05-10
申请号：JP2011266344
申请日：2011-12-05
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NAKAZAWA HARUO , SHIMOYAMA KAZUO , TAKEI MANABU
IPC分类号： H01L21/76 , H01L21/265 , H01L21/301 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a reverse-blocking type semiconductor device having a high reliability at a low cost, and a method for manufacturing the same.SOLUTION: A thin semiconductor wafer 101, on which a surface structure 133 and a rear structure 134 constructing a semiconductor chip are formed, is attached to a supporting substrate 141 with a both-sided adhesive tape 137, a trench to be a scribe line is formed on the thin semiconductor wafer 101 by exposing a crystal plane by the wet anisotropic etching, and an isolation layer 145 for keeping a reverse breakdown voltage is formed on a side face of the trench in which the crystal plane is exposed, by the ion implantation and the low temperature anneal or the laser anneal so as to contact with a p-type collector region 110 as a back diffusion layer and extend to the surface side. A collector electrode 111 is cut clean perfectly under the isolation layer 145 by laser dicing, and then the both-sided adhesive tape 137 is peeled off from the collector electrode 111 to form the semiconductor chip provided as the reverse blocking type semiconductor device.
摘要翻译：要解决的问题：提供一种低成本具有高可靠性的反向阻挡型半导体器件及其制造方法。解决方案：在其上形成有构成半导体芯片的表面结构133和后部结构134的薄半导体晶片101通过双面粘合带137，沟槽成为支撑基板141而附接到支撑基板141 通过湿式各向异性蚀刻使晶体面曝光而在薄半导体晶片101上形成刻划线，并且在其上露出晶面的沟槽的侧面上形成用于保持反向击穿电压的隔离层145，离子注入和低温退火或激光退火，以便与作为反向扩散层的p型集电区110接触并延伸到表面侧。通过激光切割将绝缘层111完全切割在隔离层145下，然后将双面胶带137从集电极111剥离，形成作为反向阻挡型半导体装置的半导体芯片。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2012089560A Method of manufacturing inverse prevention type igbt equipped with inclined side surface 审中-公开
标题翻译：装有反向预防型IGBT的方法，内置有侧面表面
公开(公告)号：JP2012089560A
公开(公告)日：2012-05-10
申请号：JP2010232476
申请日：2010-10-15
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KUBOUCHI MOTOYOSHI , SHIMIZU HIDEO , NAKAZAWA HARUO , OGINO MASAAKI
IPC分类号： H01L29/739 , H01L21/306 , H01L21/308 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an inverse prevention type IGBT equipped with an inclined side surface, causing little unwanted etching that reaches the lower side of an etching mask at the time when forming a slope on the side surface of a semiconductor chip, resulting in no contamination with etching liquid.SOLUTION: The manufacturing method includes a first step to form an MOS gate structure 10 in an element active region and an aluminum electrode film 18 on one main surface of an n-type semiconductor substrate 30 whose main surface is a (100) surface, a second step to form an ion implantation damage layer 21 with a p-type dopant as an impure substance by ion implantation or a high-concentration p-type layer 21a which is available by activating the ion implantation damage layer 21 on the other main surface, a third step to form a tapered inclined groove 23 by performing wet anisotropic etching on the other surface of the n-type semiconductor substrate, with the ion implantation damage layer or high-concentration p-type layer 21a as a mask, and a fourth step to form a p-type separation layer 4 on an inclined surface 9a constituting the inclined groove 23 by the ion implantation of the p-type dopant.
摘要翻译：要解决的问题：为了提供一种制造具有倾斜侧表面的防逆型IGBT的方法，在形成侧表面上的斜面时，几乎不需要蚀刻到达蚀刻掩模的下侧的半导体芯片，导致没有腐蚀液体的污染。解决方案：制造方法包括在元件有源区中形成MOS栅极结构10的第一步骤和主表面为（100）的n型半导体衬底30的一个主表面上的铝电极膜18，表面，通过离子注入形成具有p型掺杂剂作为不纯物质的离子注入损伤层21的第二步骤或通过在另一个上激活离子注入损伤层21可获得的高浓度p型层21a 主表面，通过在离子注入损伤层或高浓度p型层21a作为掩模在n型半导体衬底的另一个表面上进行湿式各向异性蚀刻来形成锥形倾斜槽23的第三步骤，以及通过p型掺杂剂的离子注入在构成倾斜槽23的倾斜表面9a上形成p型分离层4的第四步骤。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012069983A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012069983A
公开(公告)日：2012-04-05
申请号：JP2011253515
申请日：2011-11-21
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NAKAZAWA HARUO , IKEDA YOSHINARI , NOZAWA MASANOBU
IPC分类号： H01L21/265 , H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent breakdown voltage from lowering and contact resistance increase, while increasing the ion activation coefficient in an ion implanted layer and reducing on-voltage.SOLUTION: Cooled ion implantation 12 of BFis carried out on a back-side face 11 of a back-lapped semiconductor substrate (FZ n-type substrate 1) to form an ion-implanted layer 13 (Fig. (b)). Then, heat treatment is carried out, to form a high-concentration p-type collector layer 8 (pdiffusion layer) (Fig. (c)). This ion implantation is a cooled ion implantation for implanting the ions into the semiconductor substrate (FZ n-type substrate 1) which is cooled at liquid nitrogen temperature (-196°C). The dose quantity is set at 3×10or higher.
摘要翻译：要解决的问题：为了防止击穿电压降低和接触电阻增加，同时增加离子注入层中的离子活化系数并降低导通电压。解决方案：在背面覆盖的半导体衬底（FZ n型衬底1）的背面11上进行BF 2 的冷却离子注入12到形成离子注入层13（图（b））。然后，进行热处理，形成高浓度p型集电体层8（p（SP）=“POST”> + 扩散层）（图（c））。该离子注入是用于将离子注入到在液氮温度（-196℃）下冷却的半导体衬底（FZ n型衬底1）中的冷却离子注入。剂量设定在3×10 13 以上。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2011187916A Method of manufacturing reverse block-type insulated gate bipolar transistor 审中-公开
标题翻译：反向块式绝缘栅双极晶体管的制造方法
公开(公告)号：JP2011187916A
公开(公告)日：2011-09-22
申请号：JP2010183847
申请日：2010-08-19
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NAKAZAWA HARUO , KUBOUCHI MOTOYOSHI , TERANISHI HIDEAKI , SHIMIZU HIDEO
IPC分类号： H01L21/336 , H01L21/265 , H01L21/76 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66325 , H01L29/0619 , H01L29/402 , H01L29/66333 , H01L29/7395
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a reverse block-type insulated gate bipolar transistor capable of securing highly-reliable reverse voltage resistance, and suppressing a leakage current in reverse biasing when manufacturing a reverse block-type IGBT having a separation layer formed along a tapered surface of a V-shaped groove formed by anisotropic etching. SOLUTION: In irradiation of a flash lamp for flash lamp annealing after implantation of ions into a second conductivity-type separation layer and a second conductivity-type collector layer to form the second conductivity-type collector layer and the second conductivity-type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造能够确保高可靠性的反向电压的反向块型绝缘栅双极型晶体管的方法，并且当制造具有第二栅极型IGBT的反向块型IGBT时，可以抑制反向偏压中的漏电流沿着通过各向异性蚀刻形成的V形槽的锥形表面形成的分离层。解决方案：在将离子注入第二导电型分离层和第二导电型集电器层中以形成第二导电型集电极层和第二导电型集电极层之后，在闪光灯退火的照射中分离层，辐射能的最强部分聚焦在从锥形侧边缘表面的上部到中心部分的深度位置上。版权所有（C）2011，JPO＆INPIT

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