专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2011216818A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011216818A
公开(公告)日：2011-10-27
申请号：JP2010086030
申请日：2010-04-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OIDE HIROYUKI , IKEDA HIROAKI
IPC分类号： H01L21/56 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/561 , H01L21/565 , H01L21/568 , H01L21/67017 , H01L21/67126 , H01L23/3128 , H01L23/3135 , H01L2224/13099 , H01L2224/29011 , H01L2224/81191 , H01L2224/83104 , H01L2224/83191 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device, and to make the semiconductor device compact.SOLUTION: A method of manufacturing the semiconductor device includes: a step of supplying a supercritical fluid mixed with an under-fill material 24 into a high-pressure vessel in which a stacked unit 30 having a plurality of stacked semiconductor chips 22 is arranged; and a step of filling the under-fill material 24 in the space between the plurality of the semiconductor chips 22, by heating the stacked unit 30 placed in the high-pressure vessel and curing the under-fill material 24 infiltrated between the plurality of the semiconductor chips 22 by a polymerization reaction, while the supercritical fluid is being supplied.
摘要翻译：要解决的问题：提高半导体器件的可靠性，并使半导体器件紧凑。解决方案：一种制造半导体器件的方法包括：将与填充材料24混合的超临界流体供应到高的步骤其中布置有具有多个堆叠的半导体芯片22的堆叠单元30的压力容器; 以及通过加热放置在高压容器中的堆叠单元30并固化浸没在多个半导体芯片22之间的填充材料24的多个半导体芯片22之间的空间中的步骤半导体芯片22通过聚合反应，同时提供超临界流体。

2. 发明专利

JP2009206958A Transmission method, transmission circuit, and transmission system 有权
标题翻译：传输方式，传输电路和传输系统
公开(公告)号：JP2009206958A
公开(公告)日：2009-09-10
申请号：JP2008048313
申请日：2008-02-28
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , IKEDA HIROAKI
IPC分类号： H04L25/49 , H04L25/493
CPC分类号： H04L25/4906
摘要： PROBLEM TO BE SOLVED: To reduce a number of charging and discharging of wiring between chips per one clock cycle to reduce a consumption power without using multi power sources, such as a multi potential transmission, and without using a high speed clock or a high speed delay control required for the pulse width modulation data transmission system.
SOLUTION: In a transmission side chip 30, a counter 34 outputs a count value obtained by up-counting the eight-multiplied clock CK8 of a clock CLK to a digital comparator 35. The digital comparator 35 outputs a high level signal when the counter value is equal to or more than a value of 3-bit transmitted data from flipflops 31 to 33. A selector 37 outputs a wave-like signal which performs amplitude transition once in rising or falling during one clock cycle. An output buffer 38 outputs the signal output from the selector 37 to an exterior penetrating wiring 50 of the transmission side chip 30.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了减少每个时钟周期的芯片之间的布线的充电和放电的数量，以降低功耗而不使用多电源，例如多电位传输，并且不使用高速时钟或脉宽调制数据传输系统所需的高速延迟控制。解决方案：在发送侧芯片30中，计数器34将通过将时钟CLK的八倍时钟CK8向上计数而获得的计数值输出到数字比较器35。数字比较器35输出高电平信号计数器值等于或大于来自触发器31至33的3位发送数据的值。选择器37输出在一个时钟周期期间在上升或下降中执行幅度转换一次的波形信号。输出缓冲器38将从选择器37输出的信号输出到发送侧芯片30的外部穿透布线50.版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009129953A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009129953A
公开(公告)日：2009-06-11
申请号：JP2007300155
申请日：2007-11-20
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKA YASUHIRO , KUNO NAE , TANIE HISAFUMI , NISHI KUNIHIKO , TENMYO HIROYUKI , IKEDA HIROAKI , MIYAKE HIDEJI , ISHINO MASAKAZU , UCHIYAMA SHIRO
IPC分类号： H01L21/3205 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/12 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/2518 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce a stress occurring in the vicinity of an electrode formed in a semiconductor element and can prevent the breakage of the semiconductor element or the occurrence of defective characteristic. SOLUTION: The semiconductor device is provided with a semiconductor element 6. In the semiconductor element 6, an electrode 2 is formed penetrating the both sides of the semiconductor element 6, and the electrode 2 has a hollow wherein a stress relaxing material 1 is formed to reduce a stress occurring between the semiconductor element 6 and the electrode 2. For example, the stress relaxing material 1 is formed of a low elastic body made of a photosensitive resin, or SiO 2 , polysilicon, a conductive paste, etc. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种可以减少在形成于半导体元件中的电极附近产生的应力并能够防止半导体元件断裂或不良特性的发生的半导体器件。解决方案：半导体器件设置有半导体元件6.在半导体元件6中，形成穿过半导体元件6的两侧的电极2，并且电极2具有中空部，其中应力松弛材料1 形成为减少在半导体元件6和电极2之间产生的应力。例如，应力松弛材料1由感光树脂或SiO 2 制成的低弹性体形成，多晶硅，导电膏等。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009049051A Bonding method of semiconductor substrate and laminate manufactured thereby 审中-公开
标题翻译：半导体基板与其制造的层压板的结合方法
公开(公告)号：JP2009049051A
公开(公告)日：2009-03-05
申请号：JP2007211219
申请日：2007-08-14
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TENMYO HIROYUKI , NISHI KUNIHIKO , NAKA YASUHIRO , KUNO NAE , IKEDA HIROAKI , ISHINO MASAKAZU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/73 , H01L21/76898 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05184 , H01L2224/05568 , H01L2224/05655 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/2919 , H01L2224/73104 , H01L2224/75753 , H01L2224/8113 , H01L2224/81191 , H01L2224/81192 , H01L2224/81203 , H01L2224/81205 , H01L2224/81815 , H01L2224/831 , H01L2224/83191 , H01L2224/83203 , H01L2224/83205 , H01L2224/83856 , H01L2224/83862 , H01L2224/83871 , H01L2224/83907 , H01L2224/9211 , H01L2224/94 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/11 , H01L2224/81 , H01L2224/27
摘要： PROBLEM TO BE SOLVED: To avoid positional displacement between a connection bump on one silicon wafer and a pad on another silicon wafer due to displacement of the wafers when the wafers are coated with an adhesive and laminated.
SOLUTION: With the adhesive applied between layers of the wafers, a pattern is optically detected to provisionally align the wafers. Then, wafer positions are confirmed by a wafer transmitting method using X-rays or the like to adjust the wafer positions based on position confirmation information. An adhesive is applied and set with the wafer positions fixed. A photosetting adhesive is desirable as the adhesive. The inter-layer adhesive is set simultaneously while the bump is bonded to the pad at the heating and press-contacting step.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了避免当晶片被粘合剂涂覆并层压时，由于晶片的位移，在一个硅晶片上的连接凸块和另一个硅晶片上的焊盘之间的位置偏移。解决方案：通过将粘合剂施加在晶片的层之间，光学地检测图案以临时对准晶片。然后，通过使用X射线等的晶片传送方法来确认晶片位置，以基于位置确认信息来调整晶片位置。施加粘合剂并固定晶片位置。作为粘合剂，需要光固化粘合剂。同时设置层间粘合剂，同时在加热和压接步骤将凸块粘合到垫上。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007265548A Multilayer memory 有权
标题翻译：多层记忆
公开(公告)号：JP2007265548A
公开(公告)日：2007-10-11
申请号：JP2006090062
申请日：2006-03-29
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IKEDA HIROAKI , YAMADA JUNJI
IPC分类号： G11C11/401
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L27/0688 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a multilayer memory capable of executing a series of simultaneous operations by proper timing.
SOLUTION: A memory core layer includes a delay circuit having delay time corresponding to the operation time of each internal memory circuit part. Upon reception of a simultaneous operation signal, the memory core layer is operated according to the operation signal. The delay circuit includes an autonomous sequential activation function for sending the operation signal to a next stage after the passage of delay time. The memory core layer of the next stage is sequentially activated autonomously by proper timing to disperse a peak current during the simultaneous operation. Thus, the multilayer memory capable of achieving effective excess current dispersion and a stable operation is provided.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过适当的定时执行一系列同时操作的多层存储器。解决方案：存储核心层包括具有与每个内部存储器电路部分的操作时间相对应的延迟时间的延迟电路。在接收到同时操作信号时，根据操作信号操作存储芯层。延迟电路包括用于在延迟时间通过之后将操作信号发送到下一级的自主顺序激活功能。下一级的存储核心层通过适当的定时自主地顺序激活，以在同时操作期间分散峰值电流。因此，提供能够实现有效的过剩电流分散和稳定操作的多层存储器。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007234226A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007234226A
公开(公告)日：2007-09-13
申请号：JP2007160164
申请日：2007-06-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SENBA SEIJI , NISHIO YOJI , IKEDA HIROAKI
IPC分类号： G11C11/401
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which entry of noise superimposed on an external clock signal supplied from the outside can be prevented and cross talk noise between a DQ signal output to the outside and an external clock signal can be suppressed.
SOLUTION: The semiconductor device is provided with an external clock terminal 55-1, an output terminal 52-1, and a reversed output terminal 52-2. An external clock signal is input to the external clock terminal 55-1 from the outside. The output terminal 52-1 is arranged at the vicinity of the external clock terminal 55-1 and output a data signal DQ1 indicating data to the outside. The reversed output terminal 52-2 is arranged at the vicinity of the output terminal 52-1 and the external clock terminal 55-1 and outputs a reversed data signal DQ1B to which the data signal DQ1 is reversed to the outside.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件，其中可以防止叠加在从外部提供的外部时钟信号上的噪声的输入和输出到外部的DQ信号与外部时钟信号之间的串扰噪声可以是抑制。
解决方案：半导体器件设置有外部时钟端子55-1，输出端子52-1和反向输出端子52-2。外部时钟信号从外部输入到外部时钟端子55-1。输出端子52-1配置在外部时钟端子55-1的附近，向外部输出表示数据的数据信号DQ1。反相输出端子52-2配置在输出端子52-1和外部时钟端子55-1附近，并将与数据信号DQ1反转的反向数据信号DQ1B输出到外部。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006313607A Semiconductor chip selection method, semiconductor chip, and semiconductor integrated circuit 有权
标题翻译：半导体芯片选择方法，半导体芯片和半导体集成电路
公开(公告)号：JP2006313607A
公开(公告)日：2006-11-16
申请号：JP2005136659
申请日：2005-05-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SHIBATA KAYOKO , IKEDA HIROAKI
IPC分类号： G11C11/401 , G11C8/00 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108
CPC分类号： G11C11/407 , H01L23/5226 , H01L23/535 , H01L23/544 , H01L25/0657 , H01L2223/5444 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To reduce the number of the through-conductors less than the DRAM chips to be selected in a DRAM chip selection method. SOLUTION: The through-conductors are divided into several groups. The number of the through-conductors in a group is determined to meet the condition that the number is a prime in relation with the number of conductors in other groups. Then, each combination of the selected through-conductors when selecting a through-conductor for each group is associated with each DRAM chip. Consequently, more DRAM chips than the number of the through-conductors can be selected. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了在DRAM芯片选择方法中减少要选择的DRAM芯片的直流导体数量。
解决方案：贯通导体分为几组。确定一组中贯通导体的数量，以满足数字与其他组中导体数量相关的数字的条件。然后，当为每个组选择贯通导体时，所选择的贯通导体的每个组合与每个DRAM芯片相关联。因此，可以选择比直通导体的数量多的DRAM芯片。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006013337A Three-dimensional semiconductor device 有权
标题翻译：三维半导体器件
公开(公告)号：JP2006013337A
公开(公告)日：2006-01-12
申请号：JP2004191530
申请日：2004-06-29
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L27/00 , G11C5/06 , G11C7/18 , G11C11/401 , G11C11/41 , H01L21/8242 , H01L21/8244 , H01L25/065 , H01L27/108 , H01L27/11
CPC分类号： G11C5/063 , G11C5/02 , G11C7/18 , H01L25/0657 , H01L27/10897 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce power dissipation by reducing three-dimensional wiring capacitance of a signal transmission path in a three-dimensional semiconductor device. SOLUTION: In the three-dimensional semiconductor device, a plurality of semiconductor circuit chips 30 are laminated, and a plurality of numbers of interchip wires 50 are arranged as used of signaling between the chips. In the device, only one interchip wiring 50 is selected which becomes a path of signaling at the time of signaling, and other interchip wiring 50 is electrically isolated with switches arranged between the interchip wiring 50 and a signal line. As a result, interchip wiring capacitance concerned with charge and discharge of wiring is made into minimum. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过减小三维半导体器件中的信号传输路径的三维布线电容来降低功耗。解决方案：在三维半导体器件中，层叠多个半导体电路芯片30，并且多个芯片间线路50被布置为用于芯片之间的信令。在该装置中，仅选择一个成为信令时的信令路径的芯片间配线50，并且其他芯片间布线50与布置在芯片间布线50和信号线之间的开关电隔离。结果，使与布线的充放电相关的芯片间布线电容最小化。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2014022652A Semiconductor device and test equipment therefor, and semiconductor device test method 审中-公开
标题翻译：半导体器件及其测试设备及半导体器件测试方法
公开(公告)号：JP2014022652A
公开(公告)日：2014-02-03
申请号：JP2012161806
申请日：2012-07-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IKEDA HIROAKI
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： G01R31/2601 , G01R31/2884 , G01R31/2889 , G11C29/025 , G11C2029/5006 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To detect loose contact between bump electrodes in a layered semiconductor device by a simple method.SOLUTION: A semiconductor device comprises a semiconductor chip MC0 having a Driver circuit MD0 for driving a bump electrode FB0 and a semiconductor chip CC having a driver circuit CD for driving a bump electrode BBC. The semiconductor chips MC0, CC are layered one on the other in such a way as to make the bump electrodes FB0, BBC be electrically connected thereby to form a current path including the bump electrodes FB0, BBC. In a test mode, when the driver circuit CD drives the current path to second potential during the driver circuit MD0 drives the current path to first potential, bus fight occurs. By purposely increasing current consumption by the bus fight, a connection state of the bump electrodes can be evaluated only by monitoring a change in the current consumption.
摘要翻译：要解决的问题：通过简单的方法检测分层半导体器件中的凸起电极之间的松动接触。解决方案：半导体器件包括半导体芯片MC0，其具有用于驱动凸块电极FB0的驱动电路MD0和具有用于驱动凸起电极FB0的半导体芯片CC 用于驱动凸块电极BBC的驱动电路CD。半导体芯片MC0，CC以这样的方式层叠，以使凸块电极FB0，BBC电连接，从而形成包括凸起电极FB0，BBC的电流路径。在测试模式中，当驱动电路CD驱动当前路径到第二电位时，在驱动电路MD0将当前路径驱动到第一电位时，发生总线故障。通过有意地增加总线的电力消耗，可以仅通过监视电流消耗的变化来评估凸块电极的连接状态。

10. 发明专利

JP2011243678A Interposer and method for manufacturing the same 审中-公开
标题翻译：插件及其制造方法
公开(公告)号：JP2011243678A
公开(公告)日：2011-12-01
申请号：JP2010113067
申请日：2010-05-17
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ISHINO MASAKAZU , IKEDA HIROAKI
IPC分类号： H01L23/32 , H01L23/14
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an interposer which is easily manufactured and has a wiring pattern on both sides.SOLUTION: The interposer 10 includes a first wiring substrate 20 and a second wiring substrate 30. The first and second substrates 20 and 30 respectively include wiring patterns 22 and 32 formed on one surface, through vias 25 and 35 which are electrically connected with the wiring patterns 22 and 32, and electrodes 26 and 36 which are electrically connected with the through vias 25 and 35 and provided on a surface opposite to the surface in which the wiring patterns 22 and 32 are formed. The surface of the first wiring substrate 20 in which the electrode 26 is provided faces the surface of the second wiring substrate 30 in which the electrode 36 is provided. The electrode 26 of the first wiring substrate 20 is electrically connected with the electrode 36 of the second wiring substrate 30.
摘要翻译：要解决的问题：提供一种容易制造并且在两侧具有布线图案的插入件。解决方案：插入器10包括第一布线基板20和第二布线基板30.第一和第二基板20和30分别包括形成在一个表面上的布线图案22和32，穿过通孔25和35，电气连接与布线图案22和32以及与通孔25和35电连接并且设置在与形成布线图案22和32的表面相对的表面上的电极26和36。其中设置有电极26的第一布线基板20的表面与设置有电极36的第二布线基板30的表面相对。第一布线基板20的电极26与第二布线基板30的电极36电连接。版权所有（C）2012，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式