专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2010003724A Cooling duct structure of semiconductor device, and mounting body of semiconductor device having the same 审中-公开
标题翻译：半导体器件的冷却导管结构以及具有该半导体器件的半导体器件的安装体
公开(公告)号：JP2010003724A
公开(公告)日：2010-01-07
申请号：JP2008158857
申请日：2008-06-18
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TENMYO HIROYUKI , NISHI KUNIHIKO , NAKA YASUHIRO , KUNO NAE , IKEDA HIROAKI , ISHINO MASAKAZU , MIYAKE HIDEJI , UCHIYAMA SHIRO
IPC分类号： H01L23/473
摘要： PROBLEM TO BE SOLVED: To provide a cooling duct structure of a semiconductor device having secrecy and reduced in size and thickness, and to provide a mounting body of a semiconductor device which has the structure. SOLUTION: This cooling duct structure of a semiconductor device includes a first member 201, a second member 202 and sidewalls 203, and has a cross-sectional shape which is rectangular, comprising the first member 201, the second member 202 and the two sidewalls 203. The material of the first member 201 is a first metal. The material of parts (insides) of the second member 202 and the sidewalls 203, in contact with a cooling medium, is resin, and parts (outsides) thereof which does not contact the cooling medium are covered with a second metal, to prevent the resin from being exposed. The heat from the semiconductor device is received by a heat-receiving part 111. A conduit path 113 is partitioned by an inner wall, one side thereof is an inflow path for the medium, and the other side is an outflow path therefor. Although either of the first member 201 or the second member 202 may be brought into thermal contact with the semiconductor device, it is desirable that the first member 201, made of only a metal, be brought into thermal contact with the semiconductor device. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有保密性和尺寸和厚度的半导体器件的冷却管道结构，并提供具有该结构的半导体器件的安装体。解决方案：半导体器件的这种冷却管道结构包括第一构件201，第二构件202和侧壁203，并且具有矩形的横截面形状，包括第一构件201，第二构件202和两个侧壁203.第一构件201的材料是第一金属。与冷却介质接触的第二构件202和侧壁203的部件（内部）的材料是树脂，并且不与冷却介质接触的部件（外侧）被第二金属覆盖，以防止树脂被暴露。来自半导体器件的热量由热接收部111接收。导管路径113被内壁隔开，其一侧是用于介质的流入路径，另一侧是用于其的流出路径。尽管第一构件201或第二构件202中的任一个可以与半导体器件热接触，但是期望仅由金属制成的第一构件201与半导体器件热接触。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009099589A Wafer or circuit board and its connection structure 审中-公开
标题翻译：波形或电路板及其连接结构
公开(公告)号：JP2009099589A
公开(公告)日：2009-05-07
申请号：JP2007266716
申请日：2007-10-12
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TENMYO HIROYUKI , NISHI KUNIHIKO , NAKA YASUHIRO , KUNO NAE , IKEDA HIROAKI , ISHINO MASAKAZU , MIYAKE HIDEJI , UCHIYAMA SHIRO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00
CPC分类号： H05K1/0296 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/0657 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13099 , H01L2224/13111 , H01L2224/2518 , H01L2224/81193 , H01L2224/81801 , H01L2224/90 , H01L2225/06513 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/09 , H05K3/3436 , H05K2201/0367 , H05K2201/10674 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of keeping a certain interval between wafers or circuit boards, in three-dimensional mounting for connecting wafers or circuit boards to each other with an adhesive.
SOLUTION: A wafer (or a circuit board) for carrying out three-dimensional mounting has projections 20 arranged in a low-melting-point metal 15 electrically connecting the wafers to each other when the wafers 61 and 62 are connected to each other, the projections 20 specifying a height between the wafers 61 and 62 without being deformed in melting the low-melting-point metal 15. The connection structure of the wafers is manufactured by using the wafers having the projections at least on one wafer. In the manufactured connection structure of the wafers, the electrical connection between the wafers are carried out by the low-melting-point metals 15, and the projections for specifying the height between the wafers 61 and 62 without being deformed in melting the low-melting-point metals 15 are arranged in the low-melting-point metals 15.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够在晶片或电路板之间保持一定间隔的技术，在用粘合剂将晶片或电路板彼此连接的三维安装中。解决方案：用于进行三维安装的晶片（或电路板）具有布置在低熔点金属15中的突起20，当晶片61和62连接到每个晶片时，将晶片彼此电连接另一方面，突起20指定晶片61和62之间的高度，而不熔化低熔点金属15而变形。通过在至少一个晶片上使用具有突起的晶片来制造晶片的连接结构。在制造的晶片的连接结构中，晶片之间的电连接由低熔点金属15和用于指定晶片61和62之间的高度的突起进行，而不会熔化低熔点点金属15布置在低熔点金属15中。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2010161184A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010161184A
公开(公告)日：2010-07-22
申请号：JP2009002106
申请日：2009-01-08
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KUNO NAE , OHASHI SHIGEO , OSONE YASUO , NAKA YASUHIRO , TENMYO HIROYUKI , NISHI KUNIHIKO , IKEDA HIROAKI , ISHINO MASAKAZU , MIYAKE HIDEJI , UCHIYAMA SHIRO
IPC分类号： H01L23/473
CPC分类号： H01L24/14 , H01L23/3128 , H01L23/34 , H01L23/473 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a means for efficiently cooling a semiconductor element of a semiconductor device in which a package substrate, a semiconductor element, and a mounting substrate are stacked sequentially. SOLUTION: In the semiconductor device, a package substrate 11, a semiconductor element 131, and a mounting substrate 2 are sequentially stacked, the package substrate and the semiconductor element are electrically connected together via a primary connection bump 122; a heat-receiving part 31 of a liquid cooling module for cooling the semiconductor element that uses a liquid coolant is installed between the semiconductor element and the mounting substrate; and a plurality of secondary connection bumps 15 are installed between the package substrate and the mounting substrate. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于有效地冷却其中封装衬底，半导体元件和安装衬底被顺序堆叠的半导体器件的半导体元件的装置。解决方案：在半导体器件中，依次堆叠封装基板11，半导体元件131和安装基板2，封装基板和半导体元件经由主连接凸块122电连接在一起; 在半导体元件和安装基板之间安装用于冷却使用液体冷却剂的半导体元件的液体冷却模块的受热部31; 并且在封装基板和安装基板之间安装多个次级连接凸块15。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009129953A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009129953A
公开(公告)日：2009-06-11
申请号：JP2007300155
申请日：2007-11-20
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKA YASUHIRO , KUNO NAE , TANIE HISAFUMI , NISHI KUNIHIKO , TENMYO HIROYUKI , IKEDA HIROAKI , MIYAKE HIDEJI , ISHINO MASAKAZU , UCHIYAMA SHIRO
IPC分类号： H01L21/3205 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/12 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/2518 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce a stress occurring in the vicinity of an electrode formed in a semiconductor element and can prevent the breakage of the semiconductor element or the occurrence of defective characteristic. SOLUTION: The semiconductor device is provided with a semiconductor element 6. In the semiconductor element 6, an electrode 2 is formed penetrating the both sides of the semiconductor element 6, and the electrode 2 has a hollow wherein a stress relaxing material 1 is formed to reduce a stress occurring between the semiconductor element 6 and the electrode 2. For example, the stress relaxing material 1 is formed of a low elastic body made of a photosensitive resin, or SiO 2 , polysilicon, a conductive paste, etc. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种可以减少在形成于半导体元件中的电极附近产生的应力并能够防止半导体元件断裂或不良特性的发生的半导体器件。解决方案：半导体器件设置有半导体元件6.在半导体元件6中，形成穿过半导体元件6的两侧的电极2，并且电极2具有中空部，其中应力松弛材料1 形成为减少在半导体元件6和电极2之间产生的应力。例如，应力松弛材料1由感光树脂或SiO 2 制成的低弹性体形成，多晶硅，导电膏等。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008270641A Field-effect transistor 审中-公开
标题翻译：场效应晶体管
公开(公告)号：JP2008270641A
公开(公告)日：2008-11-06
申请号：JP2007114034
申请日：2007-04-24
申请人： Elpida Memory Inc , Hiroshima Univ , エルピーダメモリ株式会社 , 国立大学法人広島大学
发明人： SUNAMI HIDEO , OYU SHIZUNORI , MIYAKE HIDEJI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate type field-effect transistor preventing gate insulation breakdown resulted from a gate insulating film and characteristic degradation by hot carrier. SOLUTION: In a field-effect transistor whose gate electrode is insulated from a semiconductor substrate surface, gate air gap is provided at least between a gate electrode surface and the semiconductor substrate surface which is opposite to the gate electrode surface, and the gate air gap is filled with a gas. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种绝缘栅型场效应晶体管，其防止栅极绝缘膜产生的栅绝缘击穿和热载体的特性劣化。解决方案：在其栅电极与半导体衬底表面绝缘的场效应晶体管中，至少在栅电极表面和与栅电极表面相对的半导体衬底表面之间提供栅极气隙，并且门气隙充满气体。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2010073879A Field effect transistor, memory cell, and method for manufacturing field effect transistor 有权
标题翻译：场效应晶体管，存储单元和制造场效应晶体管的方法
公开(公告)号：JP2010073879A
公开(公告)日：2010-04-02
申请号：JP2008239494
申请日：2008-09-18
申请人： Elpida Memory Inc , Hiroshima Univ , エルピーダメモリ株式会社 , 国立大学法人広島大学
发明人： SUNAMI HIDEO , SUGIMURA ATSUSHI , OKUYAMA KIYOSHI , OYU SHIZUNORI , MIYAKE HIDEJI
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L21/8246 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/739 , H01L45/00
CPC分类号： H01L29/7827 , H01L27/10823 , H01L27/10873 , H01L27/11507 , H01L29/0657 , H01L29/66666
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) for preventing the active areas from being taken down or deformed in a washing step. SOLUTION: In the configuration of FET, four pillar active areas each including a part in which a channel is generated during the operation of FET are provided on the surface of a semiconductor substrate, wherein the pillar active areas are separated each other by a beam field oxide film 8, gate electrodes 11a and 11b are provided via an gate insulating film 10 so as to contact the side surfaces of the pillar active areas, an upper diffusion layer 14d corresponding to a drain electrode is provided on the top surfaces of the pillar active areas, and lower diffusion layers 9a, 9b, 9c and 9d corresponding to source electrodes are provided on the surface of the silicon substrate 1. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种场效应晶体管（FET），用于防止有源区在洗涤步骤中被取下或变形。解决方案：在FET的配置中，在半导体衬底的表面上设置四个柱状有源区，每个柱状有源区包括在FET操作期间产生沟道的部分，其中柱状有源区彼此分离，通过栅极绝缘膜10设置束场氧化膜8，栅极11a，11b，与柱状有源区的侧面接触，在漏极的上表面设置有与漏电极对应的上部扩散层14d 在硅衬底1的表面上设置支柱有源区和对应于源电极的下扩散层9a，9b，9c和9d。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2006287186A Semiconductor chip comprising porous single crystal layer and its manufacturing method 有权
标题翻译：包含多孔单晶层的半导体芯片及其制造方法
公开(公告)号：JP2006287186A
公开(公告)日：2006-10-19
申请号：JP2005361123
申请日：2005-12-14
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OYU SHIZUNORI , MIYAKE HIDEJI , HAMADA KOJI , OKONOGI KENSUKE , KOZUKI YASUSHI , WATANABE MASAHARU
IPC分类号： H01L21/02 , H01L21/306 , H01L21/322
CPC分类号： H01L21/306 , H01L21/304 , H01L21/78
摘要： PROBLEM TO BE SOLVED: To provide semiconductor chips of high reliability with less breakage.
SOLUTION: The semiconductor chip includes a semiconductor substrate comprising an impurity region and a porous single crystal layer. The impurity region is formed on a main surface of the semiconductor substrate. The porous single crystal layer is formed in an internal region on the rear surface of the semiconductor substrate. The porous crystal layer is constituted by a corroding hole continuing from the rear surface of the semiconductor substrate in the internal direction of the semiconductor substrate, and an oxide film and a single crystal part formed on the internal surface of the corroding hole.
COPYRIGHT: (C)2007,JPO&INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式