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1. 发明专利

JP2009206958A Transmission method, transmission circuit, and transmission system 有权
标题翻译：传输方式，传输电路和传输系统
公开(公告)号：JP2009206958A
公开(公告)日：2009-09-10
申请号：JP2008048313
申请日：2008-02-28
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , IKEDA HIROAKI
IPC分类号： H04L25/49 , H04L25/493
CPC分类号： H04L25/4906
摘要： PROBLEM TO BE SOLVED: To reduce a number of charging and discharging of wiring between chips per one clock cycle to reduce a consumption power without using multi power sources, such as a multi potential transmission, and without using a high speed clock or a high speed delay control required for the pulse width modulation data transmission system.
SOLUTION: In a transmission side chip 30, a counter 34 outputs a count value obtained by up-counting the eight-multiplied clock CK8 of a clock CLK to a digital comparator 35. The digital comparator 35 outputs a high level signal when the counter value is equal to or more than a value of 3-bit transmitted data from flipflops 31 to 33. A selector 37 outputs a wave-like signal which performs amplitude transition once in rising or falling during one clock cycle. An output buffer 38 outputs the signal output from the selector 37 to an exterior penetrating wiring 50 of the transmission side chip 30.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了减少每个时钟周期的芯片之间的布线的充电和放电的数量，以降低功耗而不使用多电源，例如多电位传输，并且不使用高速时钟或脉宽调制数据传输系统所需的高速延迟控制。解决方案：在发送侧芯片30中，计数器34将通过将时钟CLK的八倍时钟CK8向上计数而获得的计数值输出到数字比较器35。数字比较器35输出高电平信号计数器值等于或大于来自触发器31至33的3位发送数据的值。选择器37输出在一个时钟周期期间在上升或下降中执行幅度转换一次的波形信号。输出缓冲器38将从选择器37输出的信号输出到发送侧芯片30的外部穿透布线50.版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2006013337A Three-dimensional semiconductor device 有权
标题翻译：三维半导体器件
公开(公告)号：JP2006013337A
公开(公告)日：2006-01-12
申请号：JP2004191530
申请日：2004-06-29
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L27/00 , G11C5/06 , G11C7/18 , G11C11/401 , G11C11/41 , H01L21/8242 , H01L21/8244 , H01L25/065 , H01L27/108 , H01L27/11
CPC分类号： G11C5/063 , G11C5/02 , G11C7/18 , H01L25/0657 , H01L27/10897 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce power dissipation by reducing three-dimensional wiring capacitance of a signal transmission path in a three-dimensional semiconductor device. SOLUTION: In the three-dimensional semiconductor device, a plurality of semiconductor circuit chips 30 are laminated, and a plurality of numbers of interchip wires 50 are arranged as used of signaling between the chips. In the device, only one interchip wiring 50 is selected which becomes a path of signaling at the time of signaling, and other interchip wiring 50 is electrically isolated with switches arranged between the interchip wiring 50 and a signal line. As a result, interchip wiring capacitance concerned with charge and discharge of wiring is made into minimum. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过减小三维半导体器件中的信号传输路径的三维布线电容来降低功耗。解决方案：在三维半导体器件中，层叠多个半导体电路芯片30，并且多个芯片间线路50被布置为用于芯片之间的信令。在该装置中，仅选择一个成为信令时的信令路径的芯片间配线50，并且其他芯片间布线50与布置在芯片间布线50和信号线之间的开关电隔离。结果，使与布线的充放电相关的芯片间布线电容最小化。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2008140220A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008140220A
公开(公告)日：2008-06-19
申请号：JP2006326746
申请日：2006-12-04
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , IKEDA HIROAKI
IPC分类号： G06F12/06 , G06F12/00 , G11C11/401
CPC分类号： G06F13/1647 , G06F13/1684 , G11C7/10 , G11C7/1075 , G11C8/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suppressing deterioration of transfer efficiency of data by changing over between a writing command and a reading command and issuing them to different banks without a latency time to allow bank interleaving operation.
SOLUTION: This semiconductor device has: a memory chip provided with a plurality of banks each including at least one memory cell; and a logic chip. A data bus for transmitting/receiving writing data and reading data between the bank and the logic chip is provided corresponding to the bank. The logic chip is provided with: a writing data bus for sending the writing data to the memory chip through the data bus; a reading data bus for receiving the reading data from the memory chip through the data bus; and a switch connecting the writing data bus or the reading data bus to the data bus connected to the bank corresponding to the writing command or the reading command to the bank.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件，通过在写入命令和读取命令之间切换并且将其发布到不同的存储体而不延迟等待时间来抑制数据的传输效率的劣化，从而允许存储体交错操作。解决方案：该半导体器件具有：具有多个存储体的存储器芯片，每个存储单元包括至少一个存储单元; 和逻辑芯片。与银行对应地设置用于在存储体和逻辑芯片之间发送/接收写入数据和读取数据的数据总线。逻辑芯片设有：写入数据总线，用于通过数据总线将写入数据发送到存储器芯片; 读取数据总线，用于通过数据总线从存储器芯片接收读取数据; 以及将写入数据总线或读取数据总线连接到与写入命令对应的存储体的数据总线或读取命令的开关。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006190761A Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：JP2006190761A
公开(公告)日：2006-07-20
申请号：JP2005000591
申请日：2005-01-05
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , IKEDA HIROAKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8234 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/088 , H01L27/10
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip and a semiconductor device capable of speeding up signal transmission and preventing an increase in power consumption during the signal transmission by reducing parasitic capacitance between a wire and a semiconductor substrate. SOLUTION: The semiconductor device is provided with the semiconductor substrate, the wire at least partially embedded in the substrate to serve as a current path in which a current flows depending on a transmitted signal, an insulation film for covering a region of the wire embedded in the semiconductor substrate, and a means for applying a bias voltage to the substrate or the wire to form a depletion layer extending from an interface with the insulation film in the semiconductor substrate. Alternatively, a semiconductor layer with a different conductivity type from that of the semiconductor substrate is provided which is formed in the semiconductor substrate to surround the insulation film. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体芯片和半导体器件，其能够加速信号传输，并且通过减少线和半导体衬底之间的寄生电容来防止信号传输期间的功耗增加。解决方案：半导体器件设置有半导体衬底，线至少部分地嵌入在衬底中，用作电流路径，其中电流根据透射信号流动，用于覆盖所述半导体衬底的区域的绝缘膜埋设在半导体衬底中的线，以及用于向衬底或线施加偏置电压以形成从半导体衬底中的绝缘膜的界面延伸的耗尽层的装置。或者，提供具有与半导体衬底不同的导电类型的半导体层，其形成在半导体衬底中以围绕绝缘膜。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2009134573A Multi-chip semiconductor device and data transfer method 审中-公开
标题翻译：多芯片半导体器件和数据传输方法
公开(公告)号：JP2009134573A
公开(公告)日：2009-06-18
申请号：JP2007310921
申请日：2007-11-30
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , IKEDA HIROAKI
IPC分类号： G06F13/38 , G06F13/42 , G11C5/00 , G11C5/04 , H03K19/00
CPC分类号： H01L25/0657 , G11C5/04 , G11C29/025 , H01L24/48 , H01L24/49 , H01L2224/48137 , H01L2224/49175 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To prevent the band width of inter-semiconductor chip data transfer from being reduced even when the connection failure of inter-chip wiring is occurred in a multi-chip semiconductor device. SOLUTION: When the connection failure of two inter-chip wiring of inter-chip wiring 3c of data c and inter-chip wiring 3e of data e is clarified as the result of the connection test of inter-chip wiring, the data c and e which should have been transmitted by the inter-chip wiring 3c and 3e whose connection failure is occurred are transferred alternatively with normal data d and f to a chip 2 side by double speeds by two normal inter-chip wiring 3d and 3f respectively adjacent to the inter-chip wiring 3c and 3e whose connection failure is occurred. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使当在多芯片半导体器件中发生芯片间接线的连接故障时，也可以防止半导体芯片数据传送的带宽减小。解决方案：作为芯片间接线连接测试的结果，当数据c的芯片间接线3c和芯片间接线3e的两个芯片间接线的连接故障得到澄清时，数据由发生连接故障的芯片间线路3c和3e传送的c和e分别以正常数据d和f交替地通过两个正常的芯片间线路3d和3f以双倍的速度传送到芯片2侧与发生连接失败的芯片间配线3c，3e相邻。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006019328A Laminated semiconductor device 有权
标题翻译：层压半导体器件
公开(公告)号：JP2006019328A
公开(公告)日：2006-01-19
申请号：JP2004192763
申请日：2004-06-30
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： FUKAISHI MUNEO , SAITO HIDEAKI , HAGIWARA YASUHIKO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L25/18 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04
CPC分类号： H01L23/525 , G11C5/02 , G11C5/04 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01019 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the reduction of yield due to defective penetrated wiring in a laminated semiconductor device that is formed by stacking a plurality of semiconductor chips and uses wiring penetrating through the semiconductor chips to establish electric connection among the semiconductor chips. SOLUTION: The laminated semiconductor device includes penetrated wirings 205 and 209 penetrating through semiconductor chips 204 and 213. In this case, spare penetrated wirings 206 and 210 are arranged parallel to the penetrated wirings 205 and 209, and switch circuits 203, 207 and 211 are used to change over the transmittance route of a signal to the penetrated wiring or the spare penetrated wiring. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了防止由叠层多个半导体芯片形成的叠层半导体器件中的穿透布线不良引起的产量降低，并且使用贯穿半导体芯片的布线来建立半导体芯片之间的电连接。解决方案：层叠半导体器件包括穿透半导体芯片204和213的穿透的布线205和209.在这种情况下，备用的穿透布线206和210平行于穿透的布线205和209布置，并且开关电路203,207 和211用于将信号的透射路径改变为穿透的布线或备用的穿透布线。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006012358A Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：JP2006012358A
公开(公告)日：2006-01-12
申请号：JP2004191410
申请日：2004-06-29
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： G11C11/401 , G11C5/04 , G11C5/06 , G11C8/00 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/10
CPC分类号： G11C5/04 , G11C5/063 , H01L25/0657 , H01L2224/16145 , H01L2225/06527 , H01L2225/06555 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor memory device capable of reducing a wiring capacity required for charge and discharge at the time of data transfer, thereby reducing power consumption. SOLUTION: The memory device comprises; a plurality of memory cell array chips which are stacked on a first semiconductor chip and have sub-banks resulting from dividing bank memories collectively arranged correspondingly to input and output bits; and inter-chip wires of which the number is equal to the number of the input and output bits and which connect the memory cell array chips in a form of piercing them in the stacking direction so that the sub-banks correspond to the same corresponding input and output bits. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够减少数据传送时的充放电所需的布线容量的三维半导体存储装置，从而降低功耗。解决方案：存储器件包括：多个存储单元阵列芯片，堆叠在第一半导体芯片上，并且具有由对应于输入和输出位共同排列的划分存储体而产生的子库; 芯片间线数等于输入和输出位的数量，并将存储单元阵列芯片以堆叠方向穿透的形式连接，使得子库对应于相同的相应输入和输出位。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006012337A Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：JP2006012337A
公开(公告)日：2006-01-12
申请号：JP2004190317
申请日：2004-06-28
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , H01L21/20 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C5/025 , G11C5/02 , G11C5/063
摘要： PROBLEM TO BE SOLVED: To reduce development costs of many kinds of memory devices.
SOLUTION: This memory device has a memory cell array chip provided with a memory cell array, an interface chip which is stacked on the memory cell array chip and provided with a memory constitution switching circuit for changing an input and output bit constitution of the memory cell array, and a plurality of inter-chip wires for connecting the memory cell array chip and the interface chip.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决问题：降低多种存储器件的开发成本。解决方案：该存储器件具有设置有存储单元阵列的存储单元阵列芯片，接口芯片，其堆叠在存储单元阵列芯片上，并且具有用于改变输入和输出位构成的存储器结构切换电路存储单元阵列和用于连接存储单元阵列芯片和接口芯片的多个芯片间线。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2012008747A Integration device, memory allocation method and program 审中-公开
标题翻译：集成设备，存储器分配方法和程序
公开(公告)号：JP2012008747A
公开(公告)日：2012-01-12
申请号：JP2010143245
申请日：2010-06-24
申请人： Nec Corp , 日本電気株式会社
发明人： SAITO HIDEAKI
IPC分类号： G06F12/06 , G06F12/00 , G11C11/41 , H01L21/822 , H01L27/04
CPC分类号： H01L2924/0002 , Y02D10/13 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a memory allocation method that reduces power consumption.SOLUTION: An integration device includes: memory composed of memory macros 201-203 having a different capacity; and a semiconductor device storing, in the memory macro 201 whose capacity is smaller than the other memory macros 202 and 203 among the memory macros 201-203, data having a high frequency of write and/or read. A data processing device connected to the memory macros executes a sequence of instructions in a machine language that is finally converted from a high-level language program coded so as to allocate the data having a high frequency of write and/or read to the specific memory macro 201 on a priority basis.
摘要翻译：要解决的问题：提供降低功耗的存储器分配方法。集成装置包括：由具有不同容量的存储器宏201-203组成的存储器; 以及半导体器件，其在存储器宏201中存储容量小于存储器宏201-203中的其他存储器宏202和203的数据，具有高写入和/或读取频率的数据。连接到存储器宏的数据处理设备执行机器语言的指令序列，其最终从被编码的高级语言程序转换，以便将具有高写入和/或读取频率的数据分配给特定存储器宏201优先。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2011146944A Programmable device circuit 审中-公开
标题翻译：可编程器件电路
公开(公告)号：JP2011146944A
公开(公告)日：2011-07-28
申请号：JP2010006410
申请日：2010-01-15
申请人： Nec Corp , 日本電気株式会社
发明人： SAITO HIDEAKI
IPC分类号： H03K19/177 , H01L21/82 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a programmable device circuit which operates at high seed by minimizing a data transfer time of a switch node.
SOLUTION: A plurality of switch nodes 100 individually connected to a plurality of circuit blocks disposed in a two-dimensional array shape, are interconnected to form a two-dimensional freely variable connection network. Each of the switch nodes 100 is comprised of a precharge logic circuit which carries out a precharging operation in parallel while a circuit block performs data output. The precharge logic circuit requires much time for the precharging operation, thereby shortening a data transfer time. The precharge time overlaps a data output time of the circuit block, thereby avoiding a time loss.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供通过最小化交换节点的数据传送时间来在高种子操作的可编程设备电路。解决方案：分别连接到以二维阵列形状设置的多个电路块的多个开关节点100互连，以形成二维可自由变化的连接网络。每个开关节点100包括预充电逻辑电路，其在电路块执行数据输出时并行地执行预充电操作。预充电逻辑电路需要很多时间进行预充电操作，从而缩短数据传输时间。预充电时间与电路块的数据输出时间重叠，从而避免时间损失。版权所有（C）2011，JPO＆INPIT

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