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1. 发明专利

JP2006101465A Clamping circuit device 有权
标题翻译：钳位电路设备
公开(公告)号：JP2006101465A
公开(公告)日：2006-04-13
申请号：JP2004314012
申请日：2004-10-28
申请人： Denso Corp , 株式会社デンソー
发明人： MIZAWA MASATOYO , ISHIKAWA YASUYUKI , SUZUKI AKIRA , TEJIMA YOSHINORI , ISHIHARA HIDEAKI , MURAMATSU TOSHIJI , NASU TADASHI
IPC分类号： H03G11/02
摘要： PROBLEM TO BE SOLVED: To provide a clamping circuit device which can be constituted of fewer elements' in a simple fashion. SOLUTION: Reference voltages V1, V2 are set up by a series circuit of an FET 1, a resistor 2 and an FET 3. Gate potentials V4, V5 of FETs 7, 11 are set up, by performing addition and subtraction of these reference voltages and a reference voltage V2 generated by a bandgap reference circuit 6, respectively using an addition circuit 4 and a subtraction circuit 9. The clamp circuit device 12 is configured by connecting together a source of the one FET 7 with its drain connected with the power supply and a source of the other FET 11 with its drain being connected with the ground to an input terminal of a control IC unit 8. Thus, voltage is clamped to [V4+Vtp], when an excessive voltage of positive polarity is applied to an input terminal, and the voltage is clamped to [V5-Vtn], when an excessive voltage of negative polarity is applied. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：以简单的方式提供可由较少元件构成的钳位电路装置。
解决方案：参考电压V1，V2由FET1，电阻器2和FET3的串联电路建立。FET7,11的栅极电位V4，V5通过执行加法和减法这些参考电压和由带隙参考电路6分别使用加法电路4和减法电路9产生的参考电压V2。钳位电路器件12通过将一个FET 7的源极与其漏极连接在一起而构成电源和另一个FET 11的源极，其漏极与接地连接到控制IC单元8的输入端。因此，当正极性过大的电压为（V4 + Vtp）时，电压被钳位为[V4 + Vtp] 施加到输入端子，并且当施加负极性的过大电压时，电压被钳位到[V5-Vtn]。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2010107388A Multichip package 审中-公开
标题翻译：多媒体包
公开(公告)号：JP2010107388A
公开(公告)日：2010-05-13
申请号：JP2008280398
申请日：2008-10-30
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI , MAEDA KOICHI
IPC分类号： G01R31/28 , H01L21/822 , H01L25/04 , H01L25/18 , H01L27/04
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a multichip package capable of performing inspection simultaneously even when each supply voltage has each different potential between circuit chips.
SOLUTION: This multichip package 100 includes a plurality of circuit chips connected electrically to the inside of the package, and has an inspection mode for inspecting the circuit chips. The plurality of circuit chips include a driver chip 20, and an LSI chip 10 wherein a protection diode 11 is connected to a terminal, and a supply voltage during an inspection mode time has a lower potential than a supply voltage of the driver chip 20, and also include the first level shift circuit 33a for performing level shift of a signal from the driver chip 20 so as to have the same potential as the supply voltage of the LSI chip 10 during the inspection mode time and outputting it to the LSI chip 10.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：即使当每个电源电压在电路芯片之间具有不同的电位时，也可以提供能够同时进行检查的多芯片封装。解决方案：该多芯片封装100包括电连接到封装内部的多个电路芯片，并且具有用于检查电路芯片的检查模式。多个电路芯片包括驱动器芯片20和其中保护二极管11连接到端子的LSI芯片10，并且在检查模式时间期间的电源电压具有比驱动器芯片20的电源电压低的电位，并且还包括用于在检查模式时间期间执行来自驱动器芯片20的信号的电平移位以便具有与LSI芯片10的电源电压相同的电位的第一电平移位电路33a，并将其输出到LSI芯片10 。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2007311402A Multichip package 审中-公开
标题翻译：多媒体包
公开(公告)号：JP2007311402A
公开(公告)日：2007-11-29
申请号：JP2006136476
申请日：2006-05-16
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI
IPC分类号： H01L25/04 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To achieve a multichip package in which functional inspection of circuits connected by inter-chip wiring can be performed individually while miniaturizing the multichip package.
SOLUTION: Connection between an internal circuit 61 and external terminals 15 and 16 is switched to electrical disconnection state by a switching circuit SW5, and inter-chip wiring 41 and 42 is switched to a state connected electrically with the external terminals 15 and 16 by a switching circuit SW6. Consequently, an LIN communication control unit 53 is connected with the external terminals 15 and 16 through the inter-chip wiring 41 and 42, and the external terminals 15 and 16 can be used as terminals for inspecting the LIN communication control unit 53. Since it is not required to prepare an external terminal dedicated to inspection, the number of external terminals can be decreased as compared with a conventional multichip package and thereby the multichip package 1 can be miniaturized.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现多芯片封装，其中可以单独执行通过芯片间布线连接的电路的功能检查，同时使多芯片封装小型化。解决方案：通过开关电路SW5将内部电路61和外部端子15和16之间的连接切换到断电状态，并且芯片间接线41和42切换到与外部端子15和 16由开关电路SW6。因此，LIN通信控制单元53通过芯片间接线41和42与外部端子15和16连接，外部端子15和16可以用作用于检查LIN通信控制单元53的端子。由于它不需要准备专用于检查的外部终端，与常规的多芯片封装相比，外部端子的数量可以减少，从而可以使多芯片封装1小型化。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2012008928A Few-terminal microcomputer and inspection method thereof 审中-公开
标题翻译：微型终端微型计算机及其检测方法
公开(公告)号：JP2012008928A
公开(公告)日：2012-01-12
申请号：JP2010146287
申请日：2010-06-28
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI
IPC分类号： G06F15/78 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To provide a few-terminal microcomputer enabling short-time inspection, and an inspection method thereof.SOLUTION: A few-terminal microcomputer includes input terminals P1i and P2i and output terminals P1o and P2o that are arranged with a smaller number than the number of operating bits in a CPU 71, and is configured such that each of the input terminals P1i and P2i can independently input its serial data and each of the output terminals P1o and P2o can independently output its serial data in a test mode and a user mode. The few-terminal microcomputer 100 includes an input conversion circuit 10i that is inserted into an input path in the test mode located between an input mode switching circuit 74i and an input circuit 73i, for converting serial data of 3-or-more multilevel code to be input into serial data of binary code processable in the input circuit 73i and outputting the converted serial data.
摘要翻译：要解决的问题：提供能够进行短时间检查的多终端微型计算机及其检查方法。解决方案：多端子微计算机包括输入端子P1i和P2i以及输出端子P1o和P2o，其布置成比CPU71中的操作位数更小，并且被配置为使得每个输入端子 P1i和P2i可以独立地输入其串行数据，并且每个输出端子P1o和P2o可以在测试模式和用户模式下独立地输出其串行数据。少数终端微型计算机100包括：输入转换电路10i，其被插入到位于输入模式切换电路74i和输入电路73i之间的测试模式的输入路径中，用于将3级以上多级代码的串行数据转换为输入到可在输入电路73i中处理的二进制码的串行数据，并输出转换的串行数据。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2009272474A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2009272474A
公开(公告)日：2009-11-19
申请号：JP2008122151
申请日：2008-05-08
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method for performing marking only on defective semiconductor chips without performing marking on non-defective ones.
SOLUTION: Each semiconductor device is formed on each chip area 42 of a semiconductor wafer 40, and the inspection of the semiconductor wafer 40 is performed for each semiconductor device, Fig.2(a). After the wafer inspection, a mark 30 indicating being defective is marked on a chip area 42 on which a semiconductor device determined defective by the wafer inspection is formed out of the whole surface 41 of the semiconductor wafer 40 (see Fig.2(b)). Only defective ones can be thereby marked by the mark 30, leaving non-defective ones unmarked.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种仅在缺陷半导体芯片上进行标记而不对不良缺陷进行标记的方法。解决方案：每个半导体器件形成在半导体晶片40的每个芯片区域42上，并且对于每个半导体器件执行对半导体晶片40的检查，图2（a）。在晶片检查之后，在半导体晶片40的整个表面41上形成由芯片区域42标记的晶片检查有缺陷的半导体器件的芯片区域42（参见图2（b）），）。因此，只有有缺陷的标记可以被标记30标记，留下没有缺陷的标记。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008218887A Semiconductor device and testing method thereof 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：JP2008218887A
公开(公告)日：2008-09-18
申请号：JP2007057167
申请日：2007-03-07
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI
IPC分类号： H01L21/822 , G01R31/28 , H01L27/04
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a testing method thereof wherein complexity in configuration for testing can be reduced, in a circuit to be tested corresponding to a signal terminal in which inter-chip wiring is formed, and a test equivalent to the case of testing a single semiconductor chip can be performed.
SOLUTION: In testing an LED control section 26, analog switches 36 to 43 are switched on/off, and input/output operation functions of an input/output circuit 56 are invalidated, and a connection path from external terminals 4, 5 to the LED control section 26 is formed. In testing an LED driver 44, the analog switches 36 to 43 are switched on/off, and enables the input/output operation functions of the input/output circuit 56 are invalidated, and a connection path from external terminals 4, 5 to the LED driver 44 is formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其测试方法，其中可以减少用于测试的配置的复杂性，在与其中形成芯片间布线的信号端子对应的待测试电路中，以及可以进行相当于测试单个半导体芯片的测试的测试。解决方案：在测试LED控制部分26中，模拟开关36至43被接通/断开，输入/输出电路56的输入/输出操作功能无效，并且来自外部端子4,5的连接路径形成LED控制部26。在测试LED驱动器44中，模拟开关36至43被接通/断开，使得输入/输出电路56的输入/输出操作功能无效，以及从外部端子4,5连接到LED的连接路径形成驱动器44。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2014007372A Inspection device and manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的检查装置和制造方法
公开(公告)号：JP2014007372A
公开(公告)日：2014-01-16
申请号：JP2012243775
申请日：2012-11-05
申请人： Denso Corp , 株式会社デンソー
发明人： NASU TADASHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide an inspection device and a manufacturing method, which can perform inspection by minimizing an influence of contact resistance occurring between a probe and an electrode without causing increase in the size of an end product and successfully perform inspection of a semiconductor device in which a scribe region is highly functional.SOLUTION: An inspection device 1 comprises: a first probe 11 which is made contact with a first electrode 31 provided in a product region 21 of a semiconductor device 20; a second probe 12 which is made contact with a second electrode 32 provided in a scribe region 22; and a third probe 13 which is made contact with a third electrode 33. The inspection device 1 further comprises: a supply source 4 for flowing a current or applying a voltage via either one of the first probe 11 or the second probe 12; a first detection part 5 for detecting the current or the voltage via the other probe; and a second detection part 9 for detecting a signal input via the third electrode 33 to the third probe 13.
摘要翻译：要解决的问题：提供一种检查装置和制造方法，其可以通过最小化在探针和电极之间发生的接触电阻的影响而进行检查，而不会导致最终产品的尺寸增加，并且成功地执行半导体的检查检测装置1包括：与设置在半导体装置20的产品区域21中的第一电极31接触的第一探针11; 与设置在划线区域22中的第二电极32接触的第二探针12; 以及与第三电极33接触的第三探针13.检查装置1还包括：用于使电流流过或通过第一探针11或第二探针12中的任一个施加电压的供给源4; 用于经由另一探头检测电流或电压的第一检测部分5; 以及第二检测部9，用于检测经由第三电极33向第三探针13输入的信号。

8. 发明专利

JP2000171517A METHOD AND APPARATUS FOR MEASURING ON-RESISTANCE OF POWER MOSFET AND POWER MOSFET 失效
公开(公告)号：JP2000171517A
公开(公告)日：2000-06-23
申请号：JP34693198
申请日：1998-12-07
申请人： DENSO CORP
发明人： UEDA NOBUTADA , NASU TADASHI , ABE HIROBUMI
IPC分类号： G01R31/26 , G01R27/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To measure a value of an on-resistance highly accurately while sharing a measurement terminal necessary for measuring the on-resistance of a power MOSFET. SOLUTION: Two measurement terminals 12a and 12b are set to a power MOSFET 11, thereby sharing a terminal for measuring a current and for measuring a voltage. When the power MOSFET 11 is in an off-state, a voltage V1, V2 between a source and a drain when a current running in a forward direction to a parasitic diode 11a formed between the source and drain is 11, I2 is measured. Then, in an on-state of the power MOSFET 11, a voltage V between the source and drain when a drain current is I is measured. An on resistance value RON is obtained by calculations from these measurement results. The on-resistance value RON is measured highly accurately with influences of a contact resistance 13 being eliminated.

9. 发明专利

JP2000147073A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000147073A
公开(公告)日：2000-05-26
申请号：JP32809198
申请日：1998-11-18
申请人： DENSO CORP
发明人： NASU TADASHI
IPC分类号： H01L27/04 , G01R31/28 , G01R31/316 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To readily and with high accuracy measure a standby leak current in a digital circuit part by a method wherein there are respectively independently provided an analog power source supply terminal of an analog circuit part and a digital power source supply terminal of the digital circuit part. SOLUTION: In a digital circuit part 2 and an analog circuit part 3, a power source supply terminal 4 (digital power source supply terminal) and a ground terminal 5 are respectively independently provided, and a power source supply terminal 6 (analog power source supply terminal) and a ground terminal 7. These respective terminals 4 to 7 are disposed in a peripheral part on a semiconductor chip as a pad. As one of inspection steps prior to mounting on a lead frame, a standby leak current of the digital circuit part 2 is measured, and a functional inspection is conducted. In this case, a measuring power source 7 is connected in series with a current measuring unit 8 between the power source supply terminal 4 and a ground, and a leak current when the digital circuit part 2 is set in a standby status is measured by the current measuring unit 8.

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