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1. 发明专利

JP2004022652A Semiconductor device 有权
公开(公告)号：JP2004022652A
公开(公告)日：2004-01-22
申请号：JP2002172790
申请日：2002-06-13
申请人： Denso Corp , 株式会社デンソー
发明人： ARASHIMA YOSHISUKE , ABE HIROBUMI , BAN HIROYUKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To enable a high current to flow through bump electrodes while the bump electrodes are protected against damage caused by an excess current in a semiconductor device which is equipped with wiring lines and the bump electrodes that are connected to connection pads on a semiconductor substrate. SOLUTION: Two or more of the bump electrodes 6a are allocated for each of the source pads 2a and drain pads 2b, and they are mutually connected together through re-wiring lines 5. Therefore, on a drain side, a current flowing through the drain pad 2b from the bump electrode 6a can be set smaller in amount than the case in which the single bump electrode 6a is connected to each of the source pads 2a or the drain pads 2b through the re-wiring lines 5. On a source side, a current flowing through the bump electrode 6a from the drain pad 2b can be set smaller in amount than the above case. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004022650A Semiconductor device 审中-公开
公开(公告)号：JP2004022650A
公开(公告)日：2004-01-22
申请号：JP2002172788
申请日：2002-06-13
申请人： Denso Corp , 株式会社デンソー
发明人： ITAKURA HIROKAZU , ABE HIROBUMI , BAN HIROYUKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To make a large current flow to bump electrodes while preventing the current from concentrating on a specific electrodes in a semiconductor device having wiring and the bump electrodes connected to a connecting pad on a semiconductor wafer. SOLUTION: Rewiring 5 for connecting source pads 2a, source bump electrodes 6a, drain pads 2b and drain bump electrodes 6b is provided with a pattern (so-called solid wiring) surrounding the source bump electrodes 6a, the drain bump electrodes 6b, the source pads 2a and the drain pads 2b. As a result, the current is prevented from concentrating on the specific source bump electrode 6a or drain bump electrode 6b so that the source bump electrodes 6a and the drain bump electrodes 6b are prevented from being damaged by the concentrated current. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2000171517A METHOD AND APPARATUS FOR MEASURING ON-RESISTANCE OF POWER MOSFET AND POWER MOSFET 失效
公开(公告)号：JP2000171517A
公开(公告)日：2000-06-23
申请号：JP34693198
申请日：1998-12-07
申请人： DENSO CORP
发明人： UEDA NOBUTADA , NASU TADASHI , ABE HIROBUMI
IPC分类号： G01R31/26 , G01R27/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To measure a value of an on-resistance highly accurately while sharing a measurement terminal necessary for measuring the on-resistance of a power MOSFET. SOLUTION: Two measurement terminals 12a and 12b are set to a power MOSFET 11, thereby sharing a terminal for measuring a current and for measuring a voltage. When the power MOSFET 11 is in an off-state, a voltage V1, V2 between a source and a drain when a current running in a forward direction to a parasitic diode 11a formed between the source and drain is 11, I2 is measured. Then, in an on-state of the power MOSFET 11, a voltage V between the source and drain when a drain current is I is measured. An on resistance value RON is obtained by calculations from these measurement results. The on-resistance value RON is measured highly accurately with influences of a contact resistance 13 being eliminated.

4. 发明专利

JP2005260143A Semiconductor output circuit 有权
标题翻译：半导体输出电路
公开(公告)号：JP2005260143A
公开(公告)日：2005-09-22
申请号：JP2004072647
申请日：2004-03-15
申请人： Denso Corp , 株式会社デンソー
发明人： ARASHIMA YOSHISUKE , ABE HIROBUMI , TAKAHASHI SHIGEKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/088 , H01L29/78 , H02H9/00 , H03K17/08
CPC分类号： H03K17/0822 , H01L27/0266 , H01L29/0696 , H01L29/7816
摘要： PROBLEM TO BE SOLVED: To increase an electrostatic resistance property without complicating circuit structure. SOLUTION: When electrostatic discharge is generated to the terminal 2 of an IC 11, gate potential becomes higher at a portion on the central side of a cell region composed of a plurality of assembled single cells so that the portion is brought into an on-state by coupling by the parasitic capacitance of an MOS transistor 12. On the other hand, a current temporarily flows through a protecting circuit 13 to increase the gate potential so that the portion on the peripheral side of the cell region is also brought into the on-state. By the current limiting operation of a resistor 14, the gate potentials at the portions on the peripheral side and the central side of the cell region become equal so that the whole cell region is uniformly brought into the on-state. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高静电电阻性能而不使电路结构复杂化。解决方案：当对IC 11的端子2产生静电放电时，在由多个组装的单电池构成的电池区域的中心侧的部分处的栅极电位变高，使得该部分成为通过MOS晶体管12的寄生电容耦合而导通状态。另一方面，电流暂时流过保护电路13以增加栅极电位，使得电池区域周边侧的部分也被引入开状态。通过电阻器14的电流限制动作，在单元区域的周边侧和中央侧的部分的栅极电位变得相等，使得整个单元区域均匀地进入接通状态。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004172583A Semiconductor device 有权
公开(公告)号：JP2004172583A
公开(公告)日：2004-06-17
申请号：JP2003326508
申请日：2003-09-18
申请人： Denso Corp , 株式会社デンソー
发明人： FUKUDA YUTAKA , ABE HIROBUMI , ARASHIMA YOSHISUKE , TAKAHASHI SHIGEKI
IPC分类号： H01L21/3205 , H01L23/482 , H01L23/52 , H01L27/02 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7816 , H01L23/4824 , H01L29/0696 , H01L29/41758 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which balances current flowing to cells and does not reduce an overall tolerance dose, the semiconductor device having source cells and drain cells alternately arranged like meshes and having wirings in two upper and lower layers.
SOLUTION: Lower layer wirings 1 and 2 are constituted of stripe-like source lower layer wiring 1 and drain lower layer wiring 2 for connecting source cells 20s and drain cells 20d, which are adjacent to each other in a diagonal direction of a mesh pattern. Upper layer wirings 3 and 4 are constituted of stripe-like source upper layer wiring 3 and drain upper layer wiring 4 which are arranged so as to intersect with the lower layer wirings 1 and 2 on a plane of projection and are connected to the source lower layer wiring and the drain lower layer wiring through a via hole. The source upper layer wiring 3 and the drain upper layer wiring 4 are larger in stripe width than the source lower layer wiring 1 and the drain lower layer wiring 2, and the source upper layer wiring 3 and the drain upper layer wiring 4 are alternately arranged.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2003150255A POWER CIRCUIT 审中-公开
公开(公告)号：JP2003150255A
公开(公告)日：2003-05-23
申请号：JP2001346226
申请日：2001-11-12
申请人： DENSO CORP
发明人： SUZUKI AKIRA , ABE HIROBUMI , ISHIHARA HIDEAKI
IPC分类号： G05F1/56 , G05F1/575
摘要： PROBLEM TO BE SOLVED: To reduce current consumption. SOLUTION: A reference voltage circuit 20 and an operating amplifier 21 are operated with an output voltage Vo to be generated in a terminal 14 as a power voltage. In period where the output voltage Vo is low at starting a power source, transistors Q17 and Q14 of the starting circuit 23 are respectively turned on/off, and transistors Q12 and Q11 are sufficiently turned on. When an output voltage Vo is increased to a prescribed voltage, the transistor Q17 is turned off, and its transition to normal feedback control is set. Thus, it is possible to reduce current consumption while suppressing the generation of any unstable state at rising a power source.

7. 发明专利

JP2006129549A Load-driving semiconductor device 有权
标题翻译：负载驱动半导体器件
公开(公告)号：JP2006129549A
公开(公告)日：2006-05-18
申请号：JP2004310865
申请日：2004-10-26
申请人： Denso Corp , 株式会社デンソー
发明人： OTA KINGO , OKUDA KATSUICHI , ABE HIROBUMI
IPC分类号： H02M1/08
CPC分类号： H03K17/04206 , H03K17/0822
摘要： PROBLEM TO BE SOLVED: To secure a thermal margin of a semiconductor switching element installed for driving a load without causing an increase in the size of the element.
SOLUTION: In a state that a low-side LDMOS 16 is fully turned on, a current I1 does not flow and only a current I2 flows by the conductivity of a second diode circuit 22, since a drain voltage of the low-side LDMOS is almost zero and a first diode circuit 21 is held in a non-conductive state. When the current I2 flows, a gate voltage of the LDMOS 16 is lowered to "a voltage +Vf between a collector and an emitter of a bipolar transistor 18" (V is a voltage drop in a forward direction), to cause a rise of the drain voltage of the LDMOS 16, the first diode circuit 21 is brought into a conductive state according to the rise of the drain voltage, and thereby the current I1 is made to flow to the first diode circuit. By these operations, the drain voltage of the LDMOS 16 is fixed to "the gate voltage +3Vf of the LDMOS 16".
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了确保安装用于驱动负载的半导体开关元件的热裕度而不会引起元件的尺寸的增加。解决方案：在低侧LDMOS 16完全导通的状态下，电流I1不流动，只有电流I2由于第二二极管电路22的电导流而流过，侧LDMOS几乎为零，并且第一二极管电路21保持在非导通状态。当电流I2流动时，LDMOS 16的栅极电压降低到“双极晶体管18的集电极和发射极之间的电压+ Vf”（V是向前方向的电压降），从而引起 LDMOS16的漏极电压，第一二极管电路21根据漏极电压的上升而进入导通状态，从而使电流I1流向第一二极管电路。通过这些操作，LDMOS 16的漏极电压固定为“LDMOS 16的栅极电压+ 3Vf”。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2004266809A Operational amplifier circuit, overheat detection circuit, and comparator circuit 有权
标题翻译：操作放大器电路，过热检测电路和比较器电路
公开(公告)号：JP2004266809A
公开(公告)日：2004-09-24
申请号：JP2003373114
申请日：2003-10-31
申请人： Denso Corp , 株式会社デンソー
发明人： TSUCHIYA NAOYA , ABE HIROBUMI , OKUDA KATSUICHI
IPC分类号： G01K7/01 , H01L21/822 , H01L27/04 , H03F1/52 , H03F3/45 , H03K5/08 , H03K19/003
CPC分类号： H03F3/4508 , H03F1/52 , H03F2200/361 , H03F2200/78
摘要： PROBLEM TO BE SOLVED: To provide an operational amplifier circuit capable of fixing an output logic level to a desired level in the case that a voltage of an input signal exceeds a same mode input voltage range even when a pair of incompatible transistors are employed. SOLUTION: The operational amplifier circuit is configured to include a multi-collector transistor 101 that has collectors (1) to (3) for supplying a current and is configured such that a current I3 supplied from the collector (1) increases and a current I1 supplied from the collector (3) is unchanged when no current I2 supplied from the collector (2) flows. When the voltage of the input signal exceeds the same mode input voltage range and transistors 111 to 114 are turned off, since no current I2 flows, the current I3 increases. Thus, a transistor 219 is turned on, a transistor 220 is turned on, a transistor 221 is turned off, and a transistor 222 is turned on to fix the output of the operational amplifier to a low level. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种运算放大器电路，其能够在输入信号的电压超过相同模式输入电压范围的情况下将输出逻辑电平固定到期望电平，即使当一对不兼容的晶体管是采用。解决方案：运算放大器电路被配置为包括具有用于提供电流的集电极（1）至（3））的多集电极晶体管101，并且被配置为使得从集电极（1）提供的电流I3增加，当从集电体（2）供给的电流I2不流动时，从集电极（3）供给的电流I1不变。当输入信号的电压超过相同的模式输入电压范围时，晶体管111至114截止，由于没有电流I2流动，电流I3增加。因此，晶体管219导通，晶体管220导通，晶体管221截止，晶体管222导通，将运算放大器的输出固定为低电平。版权所有（C）2004，JPO＆NCIPI

9. 发明专利

JP2004022653A Semiconductor device 审中-公开
公开(公告)号：JP2004022653A
公开(公告)日：2004-01-22
申请号：JP2002172791
申请日：2002-06-13
申请人： Denso Corp , 株式会社デンソー
发明人： KURODA TAKAO , ABE HIROBUMI , BAN HIROYUKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of shortcircuit of wiring which is caused by stress and imperfect cutting in a semiconductor device having the wiring and bump electrodes which are connected with connection pads on a semiconductor substrate. SOLUTION: Slits 8 are arranged on a re-wiring 5 which is arranged having a pattern surrounding the bump electrodes 6a and the connection pads 2, so that generated thermal stress is dispersed by the slits 8 and can be relived even if the thermal stress is generated by difference between coefficients of thermal expansion of the re-wiring 5 and a sealing film 7. As a result, cracks which are developed on the re-wiring 5 and the sealing film 7 by thermal stress can be prevented. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004022651A Semiconductor device 审中-公开
公开(公告)号：JP2004022651A
公开(公告)日：2004-01-22
申请号：JP2002172789
申请日：2002-06-13
申请人： Denso Corp , 株式会社デンソー
发明人： ARASHIMA YOSHISUKE , ABE HIROBUMI , BAN HIROYUKI
IPC分类号： H01L23/36
CPC分类号： H01L2224/11 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve a semiconductor device in heat dissipation properties, which is equipped with a semiconductor substrate where a heating element is formed, and bump electrodes formed on the one surface of the substrate and electrically connected to the heating element and mounted on a mounting substrate. SOLUTION: The bump electrodes 6a are formed on the surface 20a of the semiconductor device 20, and dummy bumps 6b not connected to the heating element 8 are provided in a region corresponding to the region of the surface 20a where the heating element 8 is formed. By this setup, a heat dissipating path, through which the heat released from the heating element 8 on the semiconductor substrate 1 is dissipated, can be composed of a heat dissipating path where heat is transferred to the mounting substrate 9 through the bump electrodes 6a and another additional heat dissipating path where heat is transferred to the mounting substrate 9 through the dummy bumps 6b. As the result, the semiconductor device 20 can be improved in heat dissipating properties, so that the heating element 8 can be restrained from varying in characteristics. COPYRIGHT: (C)2004,JPO

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