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1. 发明专利

JP2013222851A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2013222851A
公开(公告)日：2013-10-28
申请号：JP2012094043
申请日：2012-04-17
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI
IPC分类号： H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H03B5/02 , H03K3/03 , H03K3/354
CPC分类号： H01L21/823892 , H01L27/0928
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with suppressed occurrence of clock jitter.SOLUTION: A semiconductor integrated circuit comprises: an internal circuit (30) composed of a transistor (11); and a clock generating circuit (50) that are formed on a semiconductor substrate (10). The clock generating circuit has a ring oscillator (51). The semiconductor substrate has a first conductivity type. The transistor has a first well (13) of the first conductivity type, second wells (14 and 15) of a second conductivity type formed in the first well, and a third well (16) of the first conductivity type. The two second wells formed in the one first well serve as terminals of the transistor. First wiring (93) connected to the second well (15) formed in the first well of the transistor constituting the clock generating circuit and second wiring (94) connected to the third well are each independently connected to ground members (92 and 98).
摘要翻译：要解决的问题：提供抑制时钟抖动发生的半导体集成电路。解决方案：半导体集成电路包括：由晶体管（11）组成的内部电路（30）; 以及形成在半导体衬底（10）上的时钟产生电路（50）。时钟发生电路具有环形振荡器（51）。半导体衬底具有第一导电类型。晶体管具有第一导电类型的第一阱（13），形成在第一阱中的第二导电类型的第二阱（14和15）以及第一导电类型的第三阱（16）。在第一个阱中形成的两个第二个阱用作晶体管的端子。连接到形成在构成时钟发生电路的晶体管的第一阱中的第二阱（15）的第一布线（93）和连接到第三阱的第二布线（94）各自独立地连接到接地构件（92和98）。

2. 发明专利

JP2012133924A Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：JP2012133924A
公开(公告)日：2012-07-12
申请号：JP2010283189
申请日：2010-12-20
申请人： Denso Corp , 株式会社デンソー
发明人： MORINAGA TAKESHI , ISHIKAWA YASUYUKI
IPC分类号： H05F3/02 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit which suppresses a malfunction of a circuit to be protected due to application of periodic noise while protecting the circuit to be protected from electrostatic discharge.SOLUTION: The electrostatic protection circuit for protecting a circuit to be protected from electrostatic discharge comprises: a suppression circuit for suppressing application of electrostatic discharge to the circuit to be protected; and a control circuit which turns off the driving of the suppression circuit when periodic noise having a periodically varying voltage level is applied.
摘要翻译：要解决的问题：提供一种静电保护电路，其在保护被保护的电路免受静电放电的同时，抑制由于施加周期性噪声而被保护的电路的故障。解决方案：用于保护电路免受静电放电的静电保护电路包括：抑制电路，用于抑制静电放电到被保护电路; 以及控制电路，其在施加具有周期性变化的电压电平的周期性噪声时，关闭抑制电路的驱动。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012089107A Noise resistance evaluation method of semiconductor integrated circuit and noise resistance evaluation apparatus 有权
标题翻译：半导体集成电路和噪声电阻评估装置的抗噪声评估方法
公开(公告)号：JP2012089107A
公开(公告)日：2012-05-10
申请号：JP2011139684
申请日：2011-06-23
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , MORINAGA TAKESHI , YAMAMOTO SEI , MURASE TOMOHIRO
IPC分类号： G06F17/50 , G01R31/28 , G01R31/30 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a noise resistance evaluation method with which noise resistance can be evaluated within a short time even for a large-scaled semiconductor integrated circuit.SOLUTION: A noise resistance evaluation method 100 is provided which includes a first step S11 of creating a circuit net list, a second step S12 of substituting an active element with a passive element circuit to create a substitution circuit net list, a third step S13 of extracting a control node corresponding to a control terminal of a transistor, a fourth step S14 of setting a noise injection mode, a fifth step S15 of setting noise of a predetermined frequency and calculating impedance of a path between a control node and a noise injection node which are different from each other, a sixth step S16 of creating a list of impedance in each combination of the control node, the noise injection node and the path, and a seventh step S17 of determining noise resistance of a semiconductor integrated circuit from a minimum value of impedance.
摘要翻译：要解决的问题：为了提供即使对于大规模半导体集成电路也能在短时间内评估噪声电阻的噪声电阻评估方法。解决方案：提供了一种噪声电阻评估方法100，其包括创建电路网列表的第一步骤S11，用无源元件电路代替有源元件的第二步骤S12，以创建替代电路网列表，第三步骤提取与晶体管的控制端子对应的控制节点的步骤S13，设定噪声注入模式的第四步骤S14，设定预定频率的噪声的第五步骤S15，并计算控制节点与控制节点之间的路径阻抗噪声注入节点彼此不同的第六步骤S16，在控制节点，噪声注入节点和路径的每个组合中创建阻抗列表的第六步骤S16以及确定半导体集成电路的噪声电阻的第七步骤S17 从阻抗的最小值。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2010074934A Power supply apparatus 有权
标题翻译：电源设备
公开(公告)号：JP2010074934A
公开(公告)日：2010-04-02
申请号：JP2008238972
申请日：2008-09-18
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , YAMAMOTO SEI , MURATA AKITAKA
IPC分类号： H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide a power supply apparatus for preventing that an overcurrent detecting circuit and an overvoltage detecting circuit simultaneously operate. SOLUTION: An overcurrent signal (CUT1) is input to a delay control circuit part 21 from an overcurrent detecting circuit part 18. A control signal for compulsorily stopping an operation of an overvoltage detecting circuit part 19 is generated for a first period when the overcurrent detecting circuit part 18 stops output of a power supply control circuit part 20 and a second period until prescribed time elapses from the first period by using the overcurrent signal (CUT1). The control signal is input to the overvoltage detecting circuit part 19. Thus, output of the overvoltage detecting circuit part 19 is controlled. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于防止过电流检测电路和过电压检测电路同时工作的电源装置。
解决方案：过电流信号（CUT1）从过电流检测电路部分18输入到延迟控制电路部分21.在第一时段产生用于强制停止过电压检测电路部分19的操作的控制信号，过电流检测电路部分18通过使用过电流信号（CUT1）停止电源控制电路部分20的输出和从第一周期经过规定时间的第二周期。控制信号输入到过电压检测电路部分19.因此，控制过电压检测电路部分19的输出。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2002373940A Semiconductor integrated circuit apparatus 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2002373940A
公开(公告)日：2002-12-26
申请号：JP2001181668
申请日：2001-06-15
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , ICHIKAWA KOJI , ISHIHARA HIDEAKI
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/50 , H01L23/528
CPC分类号： H01L24/06 , H01L23/50 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , Y10T307/50 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To prevent the outside leakage of noise generated in a buffer circuit of a pad for inputting and outputting a signal having a high-frequency component. SOLUTION: Power supply pads 15 are provided at four corner sections of a chip 13. Signal pads 16 for low-speed operation and signal pads 17 for high-speed operation are provided adjacent to the power supply pads 15 to form a group. Each buffer circuit 22 of the signal pads 16 and 17 receives power from common power supply wiring 23 connected to the power supply pad 15. The wiring distance between one group of power supply points 43 and one group of power supply points 44 is set longer than that between the power supply pad 15 and one group of the power supply points 43. Noise generated in the buffer circuit 22 of the signal pad 17 is attenuated by a resistor 33 of the power supply wiring 23 and a capacitor 25.
摘要翻译：要解决的问题：为了防止在用于输入和输出具有高频分量的信号的焊盘的缓冲电路中产生的噪声的外部泄漏。解决方案：电源焊盘15设置在芯片13的四个角部。用于低速操作的信号焊盘16和用于高速操作的信号焊盘17邻近电源焊盘15设置成一组。信号焊盘16和17的每个缓冲电路22从连接到电源焊盘15的公共电源布线23接收电力。一组电源点43和一组电源点44之间的布线距离设定为比在电源焊盘15和一组电源点43之间。在信号焊盘17的缓冲电路22中产生的噪声由电源布线23的电阻33和电容器25衰减。

6. 发明专利

JP2009223635A Power supply circuit 审中-公开
标题翻译：电源电路
公开(公告)号：JP2009223635A
公开(公告)日：2009-10-01
申请号：JP2008067708
申请日：2008-03-17
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , MURATA AKITAKA , YAMAMOTO SEI
IPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a power supply circuit which can suppress overshoot of output voltage when canceling a status where output current is intercepted. SOLUTION: The power supply circuit is provided with transistors T24-T26 connected mutually in parallel between a grand terminal 29 and a base of a transistor T23 which controls supply of driving current to transistors T21 and T22 which exist in an electric path between a power input terminal 28 and power supply output terminal 30. The transistors T24-T26 are turned on to drive based on abnormality detection signals Sa-Sc output when abnormality like overvoltage, overheating or overcurrent occurs. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在消除输出电流被截获的状态时抑制输出电压的过冲的电源电路。解决方案：电源电路设置有晶体管T24-T26，晶体管T24-T26并联连接在大端子29和晶体管T23的基极之间，晶体管T23控制对晶体管T21和T22的驱动电流的供给，晶体管T21和T22存在于电路电源输入端子28和电源输出端子30.当过电压，过热或过电流发生异常时，晶体管T24-T26导通，基于异常检测信号Sa-Sc输出驱动。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2005269196A Integrated circuit device 审中-公开
标题翻译：集成电路设备
公开(公告)号：JP2005269196A
公开(公告)日：2005-09-29
申请号：JP2004078247
申请日：2004-03-18
申请人： Denso Corp , 株式会社デンソー
发明人： MIZAWA MASATOYO , ISHIKAWA YASUYUKI , SUZUKI AKIRA , TEJIMA YOSHINORI , ISHIHARA HIDEAKI
IPC分类号： G06F1/04 , H03K3/03 , H03K5/00
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device which can reduce a noise level generated based on a clock signal without adding an excessive circuit. SOLUTION: In the interior of a microcomputer 41, the power supply and a ground are commonly used in a clock signal output circuit 1 which generates and outputs a multiplication clock signal by a digital PLL operation with a ring oscillator 6 and an internal circuit 42 which operates with the supplied clock signal. Thus, wiring is performed so that the power is first supplied to the internal circuit 42 by power source wiring 48 and ground wiring 49 and then supplied to the clock signal output circuit 1. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以减少基于时钟信号产生的噪声电平而不增加过多电路的集成电路装置。解决方案：在微计算机41的内部，电源和接地通常用在时钟信号输出电路1中，时钟信号输出电路1通过数字PLL操作产生并输出乘法时钟信号，其中环形振荡器6和内部电路42，其与所提供的时钟信号一起工作。因此，进行布线，使得电源首先通过电源布线48和接地布线49提供给内部电路42，然后提供给时钟信号输出电路1.版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005217869A Switch circuit including clamp function and analog multiplexer 有权
标题翻译：切换电路，包括钳位功能和模拟多路复用器
公开(公告)号：JP2005217869A
公开(公告)日：2005-08-11
申请号：JP2004023298
申请日：2004-01-30
申请人： Denso Corp , 株式会社デンソー
发明人： SUZUKI AKIRA , MIZAWA MASATOYO , ISHIKAWA YASUYUKI , TEJIMA YOSHINORI , ISHIHARA HIDEAKI
IPC分类号： H01L27/04 , H01L21/822 , H03K17/687 , H03K17/693
摘要： PROBLEM TO BE SOLVED: To provide a switch circuit including a clamp function suitable for receiving an analog voltage and enabling the layout area thereof to be reduced to the utmost, and to provide an analog multiplexer. SOLUTION: When the switch circuit is turned on, gates of transistors Q1, Q13, Q2, Q5, and Q7 all go to L, and gates of transistors Q3, Q14, Q4, Q9, and Q11 all go to H. When the switch circuit is off, a voltage state reaches as shown in the figure. A medium voltage VG1 is given to the gate of the transistor Q1 to control nodes 17, 18 so as not to receive a low voltage. A clamp circuit 13 surely keeps the transistor Q2 at an off state, and a clamp circuit 14 protects the transistor Q2 from the standpoint of the withstanding voltage. The transistor Q13 blocks a return current flowing from the clamp circuit 14 to the clamp circuit 13. The transistor Q3, clamp circuits 15, 16, and the transistor Q14 are similarly operated. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种开关电路，其包括适于接收模拟电压的钳位功能，并使其布局区域最大限度地减少，并提供模拟多路复用器。解决方案：当开关电路导通时，晶体管Q1，Q13，Q2，Q5和Q7的栅极都变为L，晶体管Q3，Q14，Q4，Q9和Q11的栅极都转到H. 当开关电路断开时，电压状态如图所示。中间电压VG1被施加到晶体管Q1的栅极以控制节点17,18以便不接收低电压。钳位电路13确保将晶体管Q2保持在断开状态，并且钳位电路14从耐受电压的角度保护晶体管Q2。晶体管Q13阻止从钳位电路14流向钳位电路13的返回电流。晶体管Q3，钳位电路15,16和晶体管Q14同样工作。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005183790A Printed-wiring board 审中-公开
标题翻译：印刷线路板
公开(公告)号：JP2005183790A
公开(公告)日：2005-07-07
申请号：JP2003424838
申请日：2003-12-22
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI
IPC分类号： H05K1/02 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a printed-wiring board capable of suppressing EMI without increasing the area of the board. SOLUTION: Separation is made in terms of high frequency, by connecting a ground wiring pattern 21b connected to a circuit block 11c of which the level of generated electromagnetic noise is relatively large to a ground wiring pattern 21a connected to respective circuit blocks 11a, 11b of which generated electromagnetic noise is relatively small via a ground wiring pattern 21c. Additionally, a place where a via hole B3 connected to the ground of a circuit block 11c is arranged is separated from a ground connection point Qb, and the respective ground wiring patterns 21a-21c are arranged so that distance L in the wiring pattern for connecting the via hole B3 to the ground connection point Qb increases. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够在不增加板的面积的情况下抑制EMI的印刷电路板。解决方案：通过将连接到其产生的电磁噪声的电平相对较大的电路块11c的接地布线图案21b连接到连接到各个电路块11a的接地布线图案21a来进行高频分离其中通过接地布线图案21c产生电磁噪声的11b较小。此外，配置有与电路块11c的接地连接的通路孔B3的地方与接地连接点Qb分离，各接地配线图形21a〜21c配置成使连接用配线图案的距离L 到接地连接点Qb的通孔B3增加。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004258869A Packaged circuit design method, packaged circuit design system and packaged circuit design program 审中-公开
标题翻译：封装电路设计方法，封装电路设计系统和封装电路设计方案
公开(公告)号：JP2004258869A
公开(公告)日：2004-09-16
申请号：JP2003047473
申请日：2003-02-25
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , ICHIKAWA KOJI
IPC分类号： G06F17/50 , H05K1/02 , H05K3/00
CPC分类号： G06F17/5036 , G06F17/5068 , H01L2924/0002 , H05K1/0231 , H05K3/0005 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To determine an optimum capacity value and an optimum arrangement position of a bypass capacity in an easy and accurate manner when the bypass capacity is provided to an IC. SOLUTION: Based on impedance of current routes (P1, P2) via the bypass capacity 4 outside the IC1 and impedance inside the IC in respect of electric source terminals 2, 3 of the IC1, noise current for flowing outside the IC1 regarding a capacity value and an arrangement position of the bypass capacity 4 is calculated and the capacity value and the arranging position of the bypass capacity 4 are determined based on the calculation result. COPYRIGHT: (C)2004,JPO&NCIPI

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