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1. 发明专利

JP2009187300A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2009187300A
公开(公告)日：2009-08-20
申请号：JP2008026712
申请日：2008-02-06
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI , FUJINO TSUYOSHI
IPC分类号： G06F1/26 , G05F1/56 , G06F1/28
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of improving noise resistance without externally attaching the element of a capacitor or the like nor stopping clock supply. SOLUTION: The semiconductor integrated circuit 1 includes a BGR circuit 17 configured so as to output a stable reference voltage V1 with high noise resistance on the basis of an external power source +B, a voltage variation suppressing means 47 monitors the variation state of internal power supply voltages V2(VDD) and V3 relative to the reference voltage V1, and when the variation exceeds an allowable range, suppresses the variation by changing the circuit constant of a power source circuit 4 for generating the internal power sources V2 and V3. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在不外部附着电容器等的元件的情况下提高耐噪声性的半导体集成电路，也不停止时钟供给。解决方案：半导体集成电路1包括：BGR电路17，被配置为基于外部电源+ B输出具有高噪声电阻的稳定的参考电压V1;电压变化抑制装置47监视变化状态的内部电源电压V2（VDD）和V3相对于参考电压V1，并且当变化超过允许范围时，通过改变用于产生内部电源V2和V3的电源电路4的电路常数来抑制变化。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009038955A Driving device 有权
标题翻译：驱动装置
公开(公告)号：JP2009038955A
公开(公告)日：2009-02-19
申请号：JP2008067709
申请日：2008-03-17
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI
IPC分类号： H02M1/08
摘要： PROBLEM TO BE SOLVED: To reduce overshoot voltage and to reduce the through-current of an output circuit. SOLUTION: Intermediate voltage forming circuits 6-8, 16-18 are prepared. Voltages varying from high potential to low potential gradually are applied to the gate of a pMOS transistor Tr9 of the output circuit 5. At the same time, voltages varying from high potential to low potential gradually are applied to the gate of an nMOS transistor Tr10 of the output circuit 5. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少过冲电压并降低输出电路的通流电流。解决方案：制备中间电压形成电路6-8,16-18。从高电位到低电位的电压逐渐被施加到输出电路5的pMOS晶体管Tr9的栅极。同时，逐渐从高电位变化到低电位的电压被施加到nMOS晶体管Tr10的栅极输出电路5.版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2001004715A OPERATION ADJUSTING AND CONTROLLING DEVICE FOR ELECTRONIC CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001004715A
公开(公告)日：2001-01-12
申请号：JP17681799
申请日：1999-06-23
申请人： DENSO CORP
发明人： ICHIKAWA KOJI , MURAMATSU TOSHIJI , NODA SHINICHI
IPC分类号： G01R31/28 , G01R31/3183 , H03F1/00
摘要： PROBLEM TO BE SOLVED: To constitute an operation adjusting and controlling device which controls the driving data given to a circuit that adjusts the operating characteristic of an electronic circuit at a lower cost. SOLUTION: A control circuit 9, a storage circuit 10, a data value deciding circuit 11, and a data outputting circuit 12 are formed on the same Si substrate 21, and driving data used for adjusting the voltage of a power source for control generated and outputted by means of an operational amplifier 2 to a prescribed value is prestored in the storage circuit 10. The timing generator of the control circuit 9 reads out the driving data from the storage circuit 10 when the operational amplifier 2 is operated, and outputs the data to an adjustment circuit 7 through the data outputting circuit 12.

4. 发明专利

JP2000357947A CLOCK CONTROL CIRCUIT 失效
公开(公告)号：JP2000357947A
公开(公告)日：2000-12-26
申请号：JP16977999
申请日：1999-06-16
申请人： DENSO CORP
发明人： NODA SHINICHI , YAMAUCHI SHIGENORI , MAEDA KOICHI , WATANABE TAKAMOTO
IPC分类号： H03K5/00 , H03K5/15
摘要： PROBLEM TO BE SOLVED: To provide a clock control circuit which can immediately start the operation of a clock synchronizing circuit, when a system is switched from a low power consumption mode to a standby mode. SOLUTION: A frequency multiplication circuit 17 counts, by a counter data latch circuit, time equivalent to the period of a reference clock signal PREF on the basis of an oscillation signal RCK outputted from a ring oscillator, generates multiplication clock signals POUT from the counting data and multiplication number setting data by using DCO and supplies them to CPU 12, a memory 13 and a gate array 14. When a low power consumption control circuit 18 receives a signal from a key detection switch 19 and sets ECU 11 to a sleep mode, a mode control signal PA is set to a low level, the oscillation operation of the ring oscillator is stopped, and the output of the multiplication clock signal POUT from the frequency multiplication circuit 17 is stopped.

5. 发明专利

JP2000349609A VOLTAGE DETECTION CIRCUIT 失效
公开(公告)号：JP2000349609A
公开(公告)日：2000-12-15
申请号：JP15804699
申请日：1999-06-04
申请人： DENSO CORP
发明人： SANTSUKO TOSHIYUKI , NODA SHINICHI , FUJII HIROSHI , MAEDA KOICHI , HAMANISHI HIDETADA
IPC分类号： H03K17/22 , H03F3/45 , H03K17/14
摘要： PROBLEM TO BE SOLVED: To prevent a voltage detection motion from being unstable due to a difference of a temperature characteristic of a gate threshold voltage of each transistor(TR) even in the case of a configuration where a power supply voltage level is detected on the basis of a difference of the gate threshold voltage of PMOS TRs forming differential pairs. SOLUTION: A differential pair 3 connected to a constant current source 4 consists of a 1st PMOS TR 1 and a 2nd PMOS TR 20 whose gate threshold voltage is higher than that of the TR 1. A current mirror circuit 10 is connected between the differential pair 3 and a ground terminal and a CMOS inverter circuit 12 is connected between a drain of the 2nd PMOS TR 20 and an output terminal 11. A voltage signal whose voltage results from dividing a power supply voltage by a voltage division circuit 13 is given to a gate of the 1st PMOS TR 1 and a voltage signal at a ground level is given to a gate of the 2nd PMOS TR 20. The gate area of the 2nd PMOS TR 20 is selected to be smaller than that of the 1st PMOS TR 1.

6. 发明专利

JP2011192289A Microcomputer 有权
标题翻译：微机
公开(公告)号：JP2011192289A
公开(公告)日：2011-09-29
申请号：JP2011091371
申请日：2011-04-15
申请人： Denso Corp , 株式会社デンソー
发明人： TEJIMA YOSHINORI , MATSUOKA TOSHIHIKO , NODA SHINICHI , TSURUTA SUSUMU , FUJII HIROSHI , ISHIHARA HIDEAKI
IPC分类号： G06F15/78 , G06F1/32
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To prevent an external device from being driven by an external signal terminal in a high-impedance state, even if a CPU is influenced by external noise in low-power consumption mode, thereby improving reliability. SOLUTION: A terminal control means outputs a signal for setting an output buffer 43A connected to an external signal terminal 42, to a high impedance state, in response to a command to be output when the CPU enters the low-power consumption mode. The output signal is given to the output buffer 43A via a logic gate 41 together with a port control signal which is output for controlling the external signal terminal 42 when the CPU is in operation. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止外部设备被高阻抗状态下的外部信号端子驱动，即使CPU受到低功耗模式下的外部噪声的影响，从而提高了可靠性。解决方案：终端控制装置响应于当CPU进入低功耗模式时输出的命令，输出用于将连接到外部信号端子42的输出缓冲器43A设置为高阻抗状态的信号。输出信号经由逻辑门41与输出用于在CPU运行时控制外部信号端子42的端口控制信号一起被提供给输出缓冲器43A。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010073546A Switch signal processor 有权
标题翻译：开关信号处理器
公开(公告)号：JP2010073546A
公开(公告)日：2010-04-02
申请号：JP2008240906
申请日：2008-09-19
申请人： Denso Corp , 株式会社デンソー
发明人： KAMIYA MASAHIRO , NODA SHINICHI
IPC分类号： H01H9/54 , B60H1/00 , B60R16/02 , H01H89/00
摘要： PROBLEM TO BE SOLVED: To provide a switch signal processor in which an erroneous operation can be prevented in the case a rotary switch and a pressing switch are mutually arranged in the vicinity.
SOLUTION: In the case either one of the rotary switch or a tact switch is operated, from that moment until an elapse of a prescribed time, the switch signal processor inhibits acceptance of an operation signal output by the other switch (Steps F1 to F3, R1 to R3). Accordingly, in the case a user operates one switch and erroneously operates another switch also, if the former operation signal is detected even a little earlier, then the latter operation signal is determined invalid so that occurrence of an unintended operation by the user can be prevented.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种切换信号处理器，其中在旋转开关和按压开关相互布置在附近的情况下可以防止错误的操作。解决方案：在旋转开关或触觉开关中的任何一个操作的情况下，从该时刻直到经过规定时间，开关信号处理器禁止接受另一个开关输出的操作信号（步骤F1 至F3，R1至R3）。因此，在用户操作一个开关并且错误地操作另一个开关的情况下，如果先前检测到前一个操作信号，则后一个操作信号被确定为无效，从而可以防止用户发生非预期的操作。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009079920A Semiconductor device, and inspection method of semiconductor device 有权
标题翻译：半导体器件和半导体器件的检测方法
公开(公告)号：JP2009079920A
公开(公告)日：2009-04-16
申请号：JP2007247440
申请日：2007-09-25
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, and an inspection method of the semiconductor device, in which an internal circuit connected to signal terminals having wiring formed between chips is inspected without increasing the number of terminals drawn-out to the outside of a package.
SOLUTION: Each output from output buffers 36-38 is set into a blocked state by controlling analog switches 39-41, and a power supply terminal 11 is set into an inspection state connected to a signal terminal 13 by controlling analog switches 42-44. Thereafter, a control signal 34 is switched into a fluctuation suppression state by stopping supply of a clock signal CK to the control signal 34. Then, an inspection voltage (3V) is supplied to a semiconductor chip 3 through external terminals 6, 7. In this case, the potential of a power supply terminal 16 is set at 5V, and the potential of a ground terminal 17 is set at 2V.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供半导体器件的半导体器件和检查方法，其中检查连接到具有在芯片之间形成的布线的信号端子的内部电路，而不增加引出到外包装。解决方案：通过控制模拟开关39-41将输出缓冲器36-38的每个输出设置为阻塞状态，并且通过控制模拟开关42将电源端子11设置为连接到信号端子13的检查状态 -44。此后，通过停止向控制信号34提供时钟信号CK，将控制信号34切换到波动抑制状态。然后，通过外部端子6,7将检查电压（3V）提供给半导体芯片3。在这种情况下，将电源端子16的电位设定为5V，将接地端子17的电位设定为2V。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008123538A Microcomputer 有权
标题翻译：微机
公开(公告)号：JP2008123538A
公开(公告)日：2008-05-29
申请号：JP2007322364
申请日：2007-12-13
申请人： Denso Corp , 株式会社デンソー
发明人： TEJIMA YOSHINORI , MATSUOKA TOSHIHIKO , NODA SHINICHI , TSURUTA SUSUMU , FUJII HIROSHI , ISHIHARA HIDEAKI
IPC分类号： G06F1/32 , G06F15/78
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer capable of reducing influence of external noise as much as possible when configured to be set to a low power consumption mode. SOLUTION: A CPU 32 of a microcomputer 31, every time a sleep mode is periodically canceled by a restart timer 36, resets a signal output level of each input/output terminal 42 and transits to the sleep mode. Accordingly, even if the CPU 32 is affected by the external noise during transition to the sleep mode to thereby change the signal output level of the input/output terminal, the output level is reset whenever the sleep mode is periodically canceled, thus reliability of the microcomputer 31 is improved. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种当配置为低功耗模式时能够尽可能地减少外部噪声的影响的微型计算机。解决方案：微型计算机31的CPU 32每当重启定时器36周期性地消除睡眠模式时，复位每个输入/输出终端42的信号输出电平并转换到睡眠模式。因此，即使在转换到休眠模式期间CPU32受到外部噪声的影响，从而改变输入/输出端子的信号输出电平，每当休眠模式被周期性地取消时，输出电平被复位，因此可靠性微型计算机31得到改进。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2004213197A Circuit device for controlling clock, microcomputer, oscillation frequency adjusting method of clock signal, oscillation circuit device, and memory interface circuit device 有权
公开(公告)号：JP2004213197A
公开(公告)日：2004-07-29
申请号：JP2002380002
申请日：2002-12-27
申请人： Denso Corp , 株式会社デンソー
发明人： MATSUOKA TOSHIHIKO , TEJIMA YOSHINORI , NODA SHINICHI , TSURUTA SUSUMU , FUJII HIROSHI , ISHIHARA HIDEAKI
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/08
摘要： PROBLEM TO BE SOLVED: To provide a clock control circuit device for improving reliability of oscillation operations, when using a first and a second two clock signals. SOLUTION: A sub-clock correcting part 6 of a clock control circuit device 21 corrects the oscillation frequency of a sub-clock signal SCLK, based on a main clock signal MCLK, and a main clock monitoring part 7 monitors the oscillation status of the main clock signal MCLK, based on the sub-clock signal SCLK. COPYRIGHT: (C)2004,JPO&NCIPI

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