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1. 发明专利

JP2010226211A Method for configuring pulse delay circuit 有权
标题翻译：配置脉冲延迟电路的方法
公开(公告)号：JP2010226211A
公开(公告)日：2010-10-07
申请号：JP2009068509
申请日：2009-03-19
申请人： Denso Corp , 株式会社デンソー
发明人： TERASAWA TOMOHITO , YAMAUCHI SHIGENORI , WATANABE TAKAMOTO
IPC分类号： H01L21/82 , H03K5/131 , H03K5/14 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： PROBLEM TO BE SOLVED: To configure a pulse delay circuit capable of reducing variations in delay time of each delay unit on a programmable logic device.
SOLUTION: In the method for configuring the pulse delay circuit, many cell strings each of which is composed of a plurality of logic cells arranged in a line are formed in an FPGA, and a delay in transmission between two logic cells belonging to the same cell string (hereafter, called as "transmission in the same cell string") is different from a delay in transmission between two logic cells belonging to different cell strings (hereafter, called as "transmission between different cell strings"). When mounting delay units R1 to Rn configuring a straight delay line on the FPGA, these delay units R1 to Tn are manually arranged. Specifically, the delay units R1 to Rn are allocated to n adjacent cell strings CC1 to CCn one by one, and further a delay unit R1 is allocated to the cell string CCi (i=1, 2, ..., n) so that the delay units R1 to Rn are arranged in the connection order.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：配置能够减少可编程逻辑器件上每个延迟单元的延迟时间变化的脉冲延迟电路。解决方案：在用于配置脉冲延迟电路的方法中，在FPGA中形成由多个排列成一行的逻辑单元组成的许多单元串，属于两个逻辑单元的传输延迟相同的单元串（以下称为“同一单元串中的传输”）不同于属于不同单元串的两个逻辑单元之间的传输延迟（以下称为“不同单元串之间的传输”）。当在FPGA上安装延迟单元R1至Rn构成直线延迟线时，这些延迟单元R1至Tn被手动布置。具体地说，将延迟单元R1〜Rn分别分配给n个相邻的单元串CC1〜CCn，并且将延迟单元R1分配给单元串CCi（i = 1,2，...，n），使得延迟单元R1至Rn按照连接顺序排列。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2009027262A A/d conversion circuit 有权
标题翻译： A / D转换电路
公开(公告)号：JP2009027262A
公开(公告)日：2009-02-05
申请号：JP2007185928
申请日：2007-07-17
申请人： Denso Corp , 株式会社デンソー
发明人： TERASAWA TOMOHITO , WATANABE TAKAMOTO
IPC分类号： H03M1/50
CPC分类号： H03M1/502
摘要： PROBLEM TO BE SOLVED: To shorten an A/D conversion time and to reduce a circuit area in a TAD-type A/D conversion circuit for achieving high resolution by latching an output of a delay unit at a plurality of different timings.
SOLUTION: A data holding circuit 5 provided in every output D1 to Dm of each delay unit DU constituting a pulse delay circuit 2 respectively latches outputs Di (i=1, 2, ..., m) of the delay unit DU by sampling clocks CK1 to CKn whose timing is different by a unit time ΔT (=Td/n) at a time. A pulse selector and an encoder 6 collectively converts hold data into numerical data by defining m×n-bit data in total obtained from each data holding circuit 5 and arranged in orders in which a change in a signal level caused when a signal pulse PA passes through can be detected as the hold data.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了缩短A / D转换时间并且通过在多个不同的定时锁存延迟单元的输出来减小用于实现高分辨率的TAD型A / D转换电路中的电路面积。解决方案：构成脉冲延迟电路2的每个延迟单元DU的每个输出D1至Dm中设置的数据保持电路5分别锁存延迟单元DU的输出Di（i = 1,2，...，m）通过每次以单位时间ΔT（= Td / n）取样定时不同的时钟CK1〜CKn。脉冲选择器和编码器6通过定义从每个数据保持电路5获得的总共m×n位数据，将保持数据集中地转换为数字数据，并且以信号脉冲PA通过时引起的信号电平变化的顺序通过可以被检测为保持数据。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2006311284A Analog-to-digital converting device 有权
标题翻译：模拟数字转换器件
公开(公告)号：JP2006311284A
公开(公告)日：2006-11-09
申请号：JP2005132209
申请日：2005-04-28
申请人： Denso Corp , 株式会社デンソー
发明人： TERASAWA TOMOHITO , WATANABE TAKAMOTO
IPC分类号： H03M1/50
CPC分类号： G04F10/005 , H03M1/14 , H03M1/207 , H03M1/502 , H03M1/60
摘要： PROBLEM TO BE SOLVED: To obtain highly accurate A/D (analog-to-digital) conversion data by making the magnitude of 1LSB of added numerical data uniform in an A/D converting device for improving a voltage resolution of the numerical data (A/D conversion result) by adding a plurality of pieces of the numerical data (A/D conversion result) acquired by using sampling clocks with phases different from one another.
SOLUTION: A delay unit 2 is composed of m×n-stage inverters INV, and a clock generation circuit 11 is composed of m delay lines DL1 to DLm comprising i×n-stage (i=1, 2, to m) inverters INV, wherein outputs of the respective delay lines DL1 to DLm are defined as sampling clocks CK1 to CKm, respectively. That is, since delay amounts of the respective delay lines DL1 to DLm are adjusted by the number of inverters INV having the same characteristic, it is possible to obtain m sampling clocks CK1 to CKm obtained by accurately shifting the phases of the sampling clocks by ΔT (Td/m) at a time.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了通过在A / D转换装置中使附加数值数据的1LSB的大小均匀地获得高精度的A / D（模拟 - 数字）转换数据，以提高数字的电压分辨率通过添加通过使用彼此不同的采样时钟获取的多个数字数据（A / D转换结果）来获得数据（A / D转换结果）。解决方案：延迟单元2由m×n级反相器INV构成，并且时钟产生电路11由m个延迟线DL1至DLm组成，包括i×n级（i = 1,2，... m ）反相器INV，其中各个延迟线DL1至DLm的输出分别被定义为采样时钟CK1至CKm。也就是说，由于通过具有相同特性的反相器INV的数量来调整各个延迟线DL1至DLm的延迟量，所以可以获得通过将采样时钟的相位精确地移位ΔT而获得的m个采样时钟CK1至CKm （Td / m）。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2003065768A Method and device for synchronous detection and sensor signal detecting device 有权
标题翻译：用于同步检测和传感器信号检测装置的方法和装置
公开(公告)号：JP2003065768A
公开(公告)日：2003-03-05
申请号：JP2001256350
申请日：2001-08-27
申请人： Denso Corp , 株式会社デンソー
发明人： WATANABE TAKAMOTO
IPC分类号： G01C19/56 , G01C19/5726 , G01C19/5755 , G01P15/09 , H03D9/00 , H03H17/02 , G01P9/04
CPC分类号： G01C19/5649 , G01P15/09 , G01P15/18
摘要： PROBLEM TO BE SOLVED: To efficiently reduce high-frequency noise caused by synchronous detection without using a low-pass filter having a large time constant. SOLUTION: In the vibration gyro having a synchronous detection part 36 for synchronous detecting a sensor signal SS0 output from a sensing element 2 with a reference signal CKD being synchronous with a monitor signal MS, the vibration gyro, in order to remove high-frequency components from a detection signal SS1 after synchronous detection, uses an analog moving average filter 40, which processes the detection signal SS1 in a moving average fashion at every period being synchronous with the reference signal CKD, without using a CR filter having a large time constant. Thereby, unnecessary noise components having the same frequencies as those of a reference signal caused by synchronous detection and its harmonies can be efficiently reduced at the infinite decay range of the analog moving average filter 40.
摘要翻译：要解决的问题：为了有效地降低由同步检测引起的高频噪声，而不使用具有大时间常数的低通滤波器。解决方案：在具有同步检测部分36的振动陀螺仪中，用于同步检测从感测元件2输出的传感器信号SS0，其中参考信号CKD与监视信号MS同步，振动陀螺仪，以便去除高频分量在同步检测后的检测信号SS1中，使用模拟移动平均滤波器40，其以与基准信号CKD同步的每个周期以移动平均方式处理检测信号SS1，而不使用具有大时间常数的CR滤波器。因此，可以在模拟移动平均滤波器40的无限衰减范围内有效地减少与由同步检测引起的参考信号和其谐波具有相同频率的不必要的噪声分量。

5. 发明专利

JP2002217758A SIGNAL LEVEL DETECTION METHOD AND DEVICE WITH FILTER FUNCTION 失效
公开(公告)号：JP2002217758A
公开(公告)日：2002-08-02
申请号：JP2001007651
申请日：2001-01-16
申请人： DENSO CORP
发明人： WATANABE TAKAMOTO
IPC分类号： H04B1/10 , H03M1/14 , H03M1/50
摘要： PROBLEM TO BE SOLVED: To provide a signal level detection method and device for eliminating a high frequency noise component from an analog input signal and detecting its signal level with high accuracy. SOLUTION: The signal level detector comprises a pulse delay circuit 10 consisting of delay units (gate circuits) 2 that sequentially delay delayed pulse Pin and transmit them and an encoder 20 that detects an arrival position of the delay pulses Pin in the pulse delay circuit 10 and generates digital data DT denoting the detected position, and an analog input signal Vin is applied to each delay unit 2 as a drive voltage. As a result, a high frequency noise component superimposed on the analog input signal Vin is cancelled by passing the delay pulse Pin through the delay units 2 within one period of a clock CK. That is, the detector has a filter function of eliminating the high frequency noise component and its output is data representing a true signal level after the filter processing.

6. 发明专利

JP2000357947A CLOCK CONTROL CIRCUIT 失效
公开(公告)号：JP2000357947A
公开(公告)日：2000-12-26
申请号：JP16977999
申请日：1999-06-16
申请人： DENSO CORP
发明人： NODA SHINICHI , YAMAUCHI SHIGENORI , MAEDA KOICHI , WATANABE TAKAMOTO
IPC分类号： H03K5/00 , H03K5/15
摘要： PROBLEM TO BE SOLVED: To provide a clock control circuit which can immediately start the operation of a clock synchronizing circuit, when a system is switched from a low power consumption mode to a standby mode. SOLUTION: A frequency multiplication circuit 17 counts, by a counter data latch circuit, time equivalent to the period of a reference clock signal PREF on the basis of an oscillation signal RCK outputted from a ring oscillator, generates multiplication clock signals POUT from the counting data and multiplication number setting data by using DCO and supplies them to CPU 12, a memory 13 and a gate array 14. When a low power consumption control circuit 18 receives a signal from a key detection switch 19 and sets ECU 11 to a sleep mode, a mode control signal PA is set to a low level, the oscillation operation of the ring oscillator is stopped, and the output of the multiplication clock signal POUT from the frequency multiplication circuit 17 is stopped.

7. 发明专利

JPH104353A A/D CONVERTER 失效
公开(公告)号：JPH104353A
公开(公告)日：1998-01-06
申请号：JP15571096
申请日：1996-06-17
申请人： DENSO CORP
发明人： NONOYAMA HAYASHI , WATANABE TAKAMOTO
IPC分类号： H03M1/52
摘要： PROBLEM TO BE SOLVED: To shorten the A/D conversion time of a voltage to be measured. SOLUTION: The A/D converter is provided with an integration device consisting of an operational amplifier 11, of a capacitor 12, and of resistors 13a, 13b and a comparator 14 that compares a center voltage Vref between a ground level and a power supply voltage VDD with an output voltage Vo of the integration device (operational amplifier 11), and the integration device integrates a voltage averaging a measured voltage Vin and the power supply voltage VDD to decrease its output voltage Vo for a prescribed time ta after an output of the comparator 14 is inverted and then the integration device integrates the ground level to increase the output voltage Vo, a time Tb from the start of integration of the ground level till the output of the comparator 14 is again inverted is measured and then the measured voltage Vin is converted into a digital voltage based on a ratio of the times as above (Tb/Ta). A coding circuit TAD 22 capable of binary-coding a time with a minimum resolution of an inverting operating time of an inverter measures the times Ta, Tb as above.

8. 发明专利

JPH09292410A PHYSICAL QUALITY DETECTOR 失效
公开(公告)号：JPH09292410A
公开(公告)日：1997-11-11
申请号：JP10831596
申请日：1996-04-26
申请人： DENSO CORP
发明人： NONOYAMA HAYASHI , YAMAUCHI SHIGENORI , WATANABE TAKAMOTO
IPC分类号： G01D5/24 , G01P15/125 , G01P15/13
摘要： PROBLEM TO BE SOLVED: To provide a physical quantity detector whose sensitivity of detection output and offset can be smoothly adjusted without increasing the size of the device. SOLUTION: A signal processing circuit 22 drives a sensor element 16 in which fixed electrodes 12 and 14 are arranged at both sides of a movable electrode 10 which is displaced in response to acceleration. And in the circuit 22, a signal generating circuit 62 generates PWM signals PA and PB, into which the ineffective control period during which either of the fixed electrodes 12 and 14 its not energized, is inserted by a predetermined proportion just in the period corresponding to the data M3 stored in a memory 26 within the effective control period during which the fixed electrodes 12 and 14 are alternately energized and the ratio of this energization is controlled so that the movable electrode 10 may be at a predetermined location. Furthermore, as the sensitivity of the sensor element 16 values according to the length of the ineffective control period which does not contribute to the location control of the movable electrode 10, the sensitivity can be adjusted merely by changing the setting values of the memory 26.

9. 发明专利

JPH09223951A DELAY CIRCUIT AND SIGNAL PROCESSOR 失效
公开(公告)号：JPH09223951A
公开(公告)日：1997-08-26
申请号：JP499296
申请日：1996-01-16
申请人： DENSO CORP
发明人： YAMAUCHI SHIGENORI , WATANABE TAKAMOTO
IPC分类号： H03K5/13 , H03K5/131 , H03L7/085 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a delay circuit with which the propagation delay time of pulse signal can be extremely easily shortened. SOLUTION: Concerning a delay circuit 2 constituted by successively connecting plural inverters L1, L2..., 2nd inverters K1, K2... are provided respectively corresponding to the respective inverters L1, L2..., the input terminal of an inverter Kn at an n-th step and the input terminal of an inverter Ln corresponding to it are mutually connected and further, the output terminal of the inverter Kn at the n-th step is connected to the input terminal of an inverter Ln+3 connected while being separated forward from the correspondent inverter Ln just for three inverters at the relevant delay circuit 2. Concerning such a delay circuit 2, since the inverting operations of inverters L4, L5... are started in advance by the outputs of the 2nd inverters K1, K2..., when an input signal SIN is inputted to the input terminal of the inverter L1 at the 1st step, the propagation delay time of the pulse signal is shortened.

10. 发明专利

JPH0968666A OPTICAL SCANNER 失效
公开(公告)号：JPH0968666A
公开(公告)日：1997-03-11
申请号：JP22363495
申请日：1995-08-31
申请人： DENSO CORP
发明人： WATANABE TAKAMOTO , OTSUKA YOSHINORI , KOMURA TSUKASA
IPC分类号： G02B26/10 , H04N1/113
摘要： PROBLEM TO BE SOLVED: To provide an optical scanner which can be made compact and which is constituted so that an optical scanning action can be excellently executed by accurately controlling the deflection angle of a light beam. SOLUTION: This optical scanner is constituted so that an angle detection signal is generated by an optical sensor disposed in front of a deflecting mirror M or a position sensor, an angle sensor and the like attached to the mirror M when the deflection angle of the light beam arrives at a prescribed angle by the vibration or the rotation of the mirror M. By a minute angle signal generation part 10, a minute angle signal is generated by multiplying a reference signal based on the reference signal synchronized with the vibration or the rotating cycle of the mirror M generated according to the angle detection signal. By a deflection angle interpolation signal generation part 12, the minute angle signal and an angle signal showing the specified deflecting angle of the light beam are inputted and a deflection angle interpolation signal for interpolating an interval between the angle detection signals is generated as the light emission timing signal of a light source.

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