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1. 发明专利

JPH0557840B2 失效
公开(公告)号：JPH0557840B2
公开(公告)日：1993-08-25
申请号：JP21472383
申请日：1983-11-15
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： G04C3/14 , H02P8/02 , H02P8/00

2. 发明专利

JPH0263381A LIQUID CRYSTAL TELEVISION SET 失效
公开(公告)号：JPH0263381A
公开(公告)日：1990-03-02
申请号：JP21375688
申请日：1988-08-30
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： H04N5/50 , H04N5/66
摘要： PURPOSE:To reduce number of components by providing a circuit generating a comparatively higher tuning voltage based on a result of applying A/D conversion to a voltage from an external variable resistor to a tuning voltage controller and providing an indicator circuit to a liquid crystal display device. CONSTITUTION:A D/A conversion circuit 29 after applying digital processing to the result of A/D conversion of an A/D conversion circuit 28 A/D-converting a voltage from an external variable resistor 27a giving a low voltage to a tuning voltage controller 2 and generating a comparatively high tuning voltage based thereupon is provided. Moreover, a liquid crystal display device 3 is provided with an indicator circuit 38 generating a signal to drive a channel indicator segment electrode based on the data from the A/D conversion circuit 28. Thus, an endless rotary variable resistor is used to attain quick channel operation, an inconvenient event of loss of a channel position due to reapplication of power is avoided and the circuit is realized with less number of components.

3. 发明专利

JPS63202185A VERTICAL SYNCHRONIZING SEPARATOR CIRCUIT 失效
公开(公告)号：JPS63202185A
公开(公告)日：1988-08-22
申请号：JP3421687
申请日：1987-02-17
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： H04N5/10
摘要： PURPOSE:To accurately separate a vertical synchronizing signal with simple constitution by restoring forcibly an output signal of an RC time constant circuit when the pulse width is narrower than the RC time constant regardless of the upward/downward input pulse so as to completely eliminate a pulse narrower than the RC time constant. CONSTITUTION:Both an input signal A and an /output signal C' in the initial state are at logical 'L' and coincident with each other, and a transmission gate (TG)6 is turned on. Since the pulse A is discident with the output C' when the input pulse A rises, the TG 6 is turned off, an output integration signal B' of the RC time constant circuit rises, but when the pulse width is narrow, the pulse rises till the level does not reach the transition point of the inverter 3, the TG 6 is turned on and the integration signal B' is retracted again to the output C'. When the pulse width is wide, the level reaches till the transition point, the inverters 3, 4 are inverted and the output C' is inverted. As a result, both the input A and output C' are coincident at logical 'H', the TG 6 is turned on and the integration signal B' is locked to the output signal C', the output C' is inverted and the new initial state is attained and the downward thin pulse is erased.

4. 发明专利

JPS6318691B2 失效
公开(公告)号：JPS6318691B2
公开(公告)日：1988-04-19
申请号：JP14630480
申请日：1980-10-21
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI , YOSHIDA MAKOTO , MOROKAWA SHIGERU
IPC分类号： G01K7/24 , G01K1/02 , G01K7/00 , G01K7/32 , G08C19/12

5. 发明专利

JPS6251876A AUTOMATIC PEDESTAL LEVEL CLAMPING CIRCUIT 失效
公开(公告)号：JPS6251876A
公开(公告)日：1987-03-06
申请号：JP19175485
申请日：1985-08-30
申请人： CITIZEN WATCH CO LTD
发明人： KAMIYA KIYOSHI , SUZUKI FUMINORI
IPC分类号： H04N5/16 , H04N5/18 , H04N5/66
摘要： PURPOSE:To obtain a small-sized clamping circuit of high utility by applying the output of a smoothing circuit to a DC stopping capacitor by a pedestal level clamping switch which is switched with a clamp pulse to adjust the pedestal level. CONSTITUTION:In case of underflow, that is, if a low luminance signal level corresponding to a dark part of a display picture does not exceed the threshold of a comparator of the least significant digit of an A/D converter 115, the first gate 104 closes the first switch to connect the smoothing circuit to VDD. In case of over flow, that is, if a luminance signal level corresponding to a light part exceeds the threshold of the most significant digit of the A/D converter 115, the second gate 105 closes the second switch 109 to connect the smoothing circuit to VSS. Thus, the output voltage of the smoothing circuit is raised for the dark picture and the DC bias of a composite video signal is raised to make the display picture lighter, and the DC bias is reduced for the light picture to make the display picture darker.

6. 发明专利

JPS60120612A ONE-SHOT CIRCUIT 失效
公开(公告)号：JPS60120612A
公开(公告)日：1985-06-28
申请号：JP22824183
申请日：1983-12-02
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： H03K3/033 , H03K5/05
摘要： PURPOSE:To generate a one-shot signal securely by providing an RS latch which delays a necessary frequency signal and an RS latch which decides on the pulse width of the one-shot signal. CONSTITUTION:Flip-flops 12-15 constitute a frequency dividing circuit and a signal R1 leads a signal S1 by the time corresponding to the total delay of the FFs, so the 1st RS latch 3 operates securely to output a signal S2 generated by delaying the negative edge of the signal S1 by the pulse width of the signal R1; and the signals S2 and R2 are passed through the 2nd RS latch 4 to output a signal T2. Then, the signal S1 and signal T2 are ANDed by an AND gate 5 to obtain a signal P2 which is in phase and has the same time width with the signal R2, and the influence of wiring delay due to electrostatic capacity is prevented to prevent the generation of a whisker-shaped noise.

7. 发明专利

JPS60113698A LOAD COMPENSATING CIRCUIT FOR MOTOR 失效
公开(公告)号：JPS60113698A
公开(公告)日：1985-06-20
申请号：JP22121183
申请日：1983-11-24
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： G04C3/14 , H02P8/02
摘要： PURPOSE:To reduce the size of a battery by applying a strobe pulse and judging the load of a motor from the waveform of the induced voltage, thereby largely reducing the number of additional pulse outputs. CONSTITUTION:A strobe pulse forming circuit 71 which outputs a strobe pulse group formed of 2-phase half-period-displaced pulse group for severl milli-seconds to several tens milli-seconds immediately after the motor drive pulse, a motor driver circuit 80 in which two output terminals alternately become high impedance state by the strobe pulse group are provided, the positive or negative of the polarity of the induced voltage is discriminated, patterned by a patterning circuit 72, the magnitude of the motor load is divided into three levels from the induced voltage pattern by a pattern discriminator 73, and the pulse width of the motor drive pulse or the chopper ratio is controlled with the reference level set at the intermediate as a target pattern.

8. 发明专利

JPS60109790A LOAD COMPENSATING CIRCUIT FOR MOTOR 失效
公开(公告)号：JPS60109790A
公开(公告)日：1985-06-15
申请号：JP21472483
申请日：1983-11-15
申请人： CITIZEN WATCH CO LTD
发明人： SUZUKI FUMINORI
IPC分类号： G04C3/14 , H02P8/02
摘要： PURPOSE:To reduce the size of a battery by applying a strobe pulse to judge the motor load from the induced voltage waveform, thereby largely reducing the output times of an additional pulse. CONSTITUTION:A strobe pulse forming circuit 71 for outputting strobe pulse group formed of pulse groups of two phases displaced by half period from each other for several milliseconds several tens milliseconds immediately after a motor drive pulse, and a motor driver 80 in which two output terminals alternately become high impedance state by the strobe pulse group are provided. The polarity of the induced electromotive force is discriminated by an induced voltage patterning circuit 72, and patterned, compared with a reference pattern by a pattern discriminator 73, and the output signals of the circuits 72, 73 are inputted to a control signal forming circuit 74. Then, signals UP, DN, HRY for controlling the pulse width of a motor drive pulse Pm and a chopper ratio are formed by the circuit 74.

9. 发明专利

JPS59191926A Time constant feedback type oscillating circuit 失效
标题翻译：时间恒定反馈型振荡电路
公开(公告)号：JPS59191926A
公开(公告)日：1984-10-31
申请号：JP6524483
申请日：1983-04-15
申请人： Citizen Watch Co Ltd
发明人： SUZUKI FUMINORI
IPC分类号： H03K3/354 , H03K3/0231
CPC分类号： H03K3/0231
摘要： PURPOSE:To reduce greatly the through-current of an inverter and to ensure the actuation with a small amount of current consumption by applying the signal given from an RC time constant circuit to the inverter after converting it into a rectangular wave by a voltage comparator. CONSTITUTION:An output signal V2 of an RC time constant circuit 10 is applied to a voltage comparator 11, and levels 0 and 1 are delivered when the signal V2 is lower and higher than the reference voltage Vref, respectively. As a result, the signal V2 is converted into a rectangular wave and sent to an inverter 15. Thus the through-currents of inverters 13-15 are greatly reduced. The comparator 11 consists of a voltage regulator part 11a, a voltage comparing part 11b and a waveform shaping part 11c. While the circuit 10 is provided with capacitors 10a and 10b and a p well resistance 10c, and the voltage is applied to the resistance 10c by the inverter 13.
摘要翻译：目的：为了大大减少逆变器的通电流，并且通过将由RC时间常数电路给出的信号施加到逆变器，通过电压比较器将其转换成矩形波，确保使用少量的电流消耗。构成：RC时间常数电路10的输出信号V2被施加到电压比较器11，并且当信号V2分别低于参考电压Vref时，电平0和1被递送。结果，信号V2被转换为矩形波并被发送到逆变器15.因此，逆变器13-15的通电电流大大降低。比较器11由电压调节器部分11a，电压比较部分11b和波形整形部分11c组成。在电路10设置有电容器10a，10b和p阱电阻10c的同时，由逆变器13向电阻10c施加电压。

10. 发明专利

JPS58186839A Parallel adding circuit 失效
标题翻译：并联电路
公开(公告)号：JPS58186839A
公开(公告)日：1983-10-31
申请号：JP6844782
申请日：1982-04-23
申请人： Citizen Watch Co Ltd
发明人： SUZUKI FUMINORI
IPC分类号： G06F7/505 , G06F7/50 , G06F7/506 , G06F7/53 , G06F7/60
CPC分类号： G06F7/50
摘要： PURPOSE:To shorten an operation time and to simplify circuit constitution by constituting a counter in such a way that the FF output signal of each precedent stage and a clock signal is ORed exclusively and the resulting signal is inputted to the FF of the trailing stage. CONSTITUTION:A parallel adding circuit 1 consists of the adding counter 11 constituted by connecting FFs F1-F6 in series through exclusive OR gates E2- E6 and a bus line driving circuit 12. The circuit 12 has AND gates A1-A6 which are wired so that the respective bits of parallel data from a register 2 are applied to one-side input terminals; and a common clock signal is inputted to the other-side input terminals of those AND gates. Assuming that 10111, i.e. 23 is set in the register 2, the clock signal is outputted from only the gates A1, A2, A3, and A5. Therefore, the F1, F2, F3, and F5 are set by the 1st clock signal to add 23. Then, every time a clock signal is applied, 23 is added.
摘要翻译：目的：通过构成计数器来缩短操作时间并简化电路结构，使得每个先级阶段的FF输出信号和时钟信号被独占或并入，并将结果信号输入到后级的FF。构成：并行加法电路1由通过异或门E2-E6和总线驱动电路12串联连接FF1F-F6构成的加法计数器11构成。电路12具有与之相连的与门A1-A6 来自寄存器2的并行数据的相应位被施加到单侧输入端子; 并且公共时钟信号被输入到这些与门的另一侧输入端。假设在寄存器2中设置了10111（即23），则仅从门A1，A2，A3和A5输出时钟信号。因此，F1，F2，F3和F5由第一个时钟信号设置为23。然后，每次应用时钟信号时，都会添加23。

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