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81. 发明专利

JP2011238674A Wiring board, piezoelectric oscillator, gyro sensor, and method for manufacturing wiring board 有权
标题翻译：接线板，压电振荡器，陀螺传感器及制造接线板的方法
公开(公告)号：JP2011238674A
公开(公告)日：2011-11-24
申请号：JP2010107007
申请日：2010-05-07
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： YODA TAKESHI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/76898 , B81B7/0006 , B81B2201/0242 , B81B2201/0271 , G01C19/56 , G01C19/5776 , H01L21/76877 , H01L23/481 , H01L2924/00 , H01L2924/0002 , H05K3/225 , H05K3/321 , H05K3/4038 , H05K3/429 , H05K3/462 , Y10T29/49126 , Y10T29/49128 , Y10T29/49139
摘要： PROBLEM TO BE SOLVED: To provide a wiring board, a piezoelectric oscillator, a gyro sensor, and a method for manufacturing the wiring board.SOLUTION: There are included a base substrate 12 having a first plane (surface 12a) and a second plane (reverse side 12b), a first insulation layer 14 laminated on the first plane, a pad electrode 16 laminated on the first insulation layer 14, a through electrode 20 connected to the pad electrode 16, and a second insulation layer 24 provided between the base substrate 12 and the first insulation layer 14. The diameter of the through electrode 20 at a connecting section (bottom section 22a) where it connects to the pad electrode 16 is smaller than that of the through electrode 20 on the second plane. In a peripheral region of a connecting section (bottom section 22a) where the through electrode 20 and the pad electrode 16 connect, the first insulation layer 14 and the second insulation layer 24 and the through electrode 20 overlap in a plan view, and the thickness of the first insulation layer 14a in the peripheral region is thinner than that of the first insulation layer 14 in other regions.
摘要翻译：要解决的问题：提供一种布线板，压电振荡器，陀螺仪传感器及其制造方法。解决方案：包括具有第一平面（表面12a）和第二平面（反面12b）的基底基板12，层压在第一平面上的第一绝缘层14，层压在第一绝缘层上的焊盘电极16 层14，连接到焊盘电极16的通孔电极20，以及设置在基底基板12和第一绝缘层14之间的第二绝缘层24.在连接部分（底部22a）处的通孔20的直径其连接到焊盘电极16的尺寸小于第二平面上的贯通电极20。在贯通电极20和焊盘电极16连接的连接部（底部22a）的周边区域中，第一绝缘层14和第二绝缘层24以及贯通电极20在平面图中重叠，厚度在周边区域中的第一绝缘层14a的厚度比其他区域中的第一绝缘层14薄。版权所有（C）2012，JPO＆INPIT

82. 发明专利

JP2011194478A Semiconductor dynamics quantity sensor and method of manufacturing the same 有权
标题翻译：半导体动力学量子传感器及其制造方法
公开(公告)号：JP2011194478A
公开(公告)日：2011-10-06
申请号：JP2010060565
申请日：2010-03-17
申请人： Denso Corp , 株式会社デンソー
发明人： FUJII TETSUO , GOTO KEISUKE
IPC分类号： B81C3/00 , B81B3/00 , G01P15/08 , G01P15/125 , H01L29/84
CPC分类号： G01P15/0802 , B81B7/0006 , B81B2201/0235 , B81B2203/0307 , B81B2207/095 , G01P15/125 , G01P2015/0814 , G01P2015/0877 , G01P2015/088 , H01L2224/48463
摘要： PROBLEM TO BE SOLVED: To shorten a manufacturing process and simplify a laminating structure for a semiconductor dynamics quantity sensor configured by sticking two substrates.SOLUTION: A pattern section 130 including a wiring pattern 133 and a periphery pattern 134 is formed on a first semiconductor substrate 120, and a support substrate 140 in which a first electrically insulating layer 144 is formed on a second semiconductor substrate 142 is prepared. The wiring pattern 133 and the periphery pattern 134 are directly jointed to the first electrically insulating layer 144 to stick the first semiconductor substrate 120 to the support substrate 140 to each other. Then, a sensor structure 110 is formed in the first semiconductor substrate 120 to joint a cap 200 to a periphery 150. First to fourth through electrodes 300-330 are formed at the cap 200, thus completing the semiconductor dynamics quantity sensor.
摘要翻译：要解决的问题：缩短制造工艺并简化通过粘贴两个基板构成的半导体动力学量传感器的层叠结构。解决方案：包括布线图案133和外围图案134的图案部分130形成在第一半导体基板制备在第二半导体衬底142上形成第一电绝缘层144的支撑衬底140。布线图案133和周边图案134直接接合到第一电绝缘层144，以将第一半导体衬底120彼此粘附到支撑衬底140。然后，在第一半导体衬底120中形成传感器结构110以将盖200接合到周边150.在盖200处形成第一至第四贯通电极300-330，从而完成半导体动力学量传感器。

83. 发明专利

JP2011097059A Interconnect structure provided with cavity having at least one contact rise on cavity wall and method for forming the interconnect structure 审中-公开
标题翻译：具有至少一个接缝上的孔的互连结构和形成互连结构的方法
公开(公告)号：JP2011097059A
公开(公告)日：2011-05-12
申请号：JP2010240640
申请日：2010-10-27
申请人： Commissariat A L'energie Atomique & Aux Energies Alternatives , コミッサリアアレネルジーアトミークエオゼネルジザルタナテイヴ
发明人： BOLIS SEBASTIEN , JACQUET FABRICE , SAINT-PATRICE DAMIEN
IPC分类号： H01L23/02 , H01L23/14 , H01L23/15 , H01L23/32
CPC分类号： B81B7/0006 , B81B2203/0353 , B81B2207/012 , B81B2207/07 , H01L23/481 , H01L23/5389 , H01L27/14618 , H01L27/14627 , H01L2924/0002 , H05K1/0219 , H05K1/183 , H05K3/403 , H05K3/4697 , H05K2201/09172 , H05K2201/09181 , H05K2201/09645 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a new interconnect structure that facilitates packaging without the drawbacks that the interconnect structure must be situated near the edges of a support and a method for forming the interconnect structure.
SOLUTION: The invention concerns an interconnect device comprising a support (200) in which at least one hole is formed, the hole including: walls forming a closed contour and being formed by a cavity (203); and one or several slots (205a-205b, 215a-215b) communicating with the cavity, the slots extending in a direction making a non-zero angle with the main plane of the support, several conducting elements (214) being disposed on at least one wall of the hole so as to penetrate a hole portion, the conducting elements being each intended to connect conductive areas located on either side of the support, and at least one of the slots separating two of the conductive elements.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种便于封装的新的互连结构，而不需要互连结构必须位于支撑体的边缘附近的缺点以及用于形成互连结构的方法。解决方案：本发明涉及一种互连装置，其包括其中形成有至少一个孔的支撑件（200），所述孔包括：形成封闭轮廓的壁并由腔（203）形成; 以及与空腔连通的一个或多个狭槽（205a-205b，215a-215b），所述狭槽在与所述支撑件的主平面成非零角度的方向上延伸，至少设置有几个导电元件（214）所述孔的一个壁穿过孔部分，所述导电元件各自用于连接位于所述支撑件的任一侧上的导电区域，以及分隔两个所述导电元件的所述狭槽中的至少一个。版权所有（C）2011，JPO＆INPIT

85. 发明专利

JP2009543086A At least it is distributed on two non-parallel planar integrated circuit and a method of manufacturing the same 审中-公开
公开(公告)号：JP2009543086A
公开(公告)日：2009-12-03
申请号：JP2009518927
申请日：2007-07-11
申请人：コミサリヤ・ア・レネルジ・アトミク
发明人：アルベルテイーニ，ジヤン−バテイスト
IPC分类号： G01R33/02 , G01R33/04 , G01R33/07 , G01R33/09 , H01L21/60 , H01L21/822 , H01L25/00 , H01L27/04 , H01L43/00 , H01L43/02 , H01L43/04 , H01L43/06 , H01L43/08
CPC分类号： B81B7/0006 , B81B7/0074 , B81B2201/0292 , B82Y25/00 , G01R33/0206 , G01R33/07 , G01R33/093 , H01L24/16 , H01L24/37 , H01L24/38 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/37147 , H01L2224/37599 , H01L2224/41 , H01L2224/45144 , H01L2224/48137 , H01L2224/49111 , H01L2924/00014 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/10252 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , Y10T29/41 , H01L2224/45147 , H01L2924/00 , H01L2224/45099 , H01L2224/0401
摘要：本発明は、プレート状の第１の部分（３０）を含む集積回路に関する。この構成要素はまた、第１の部分（３０）とは別の、第１の部分（３０）に取り付けられ、変形可能な接続手段（２２）によって第１の部分（３０）に接続され、第１の部分（３０）との間で非ゼロの角度を形成する少なくとも１つのプレート状の第２の部分（３２）を含む。

86. 发明专利

JP2009534819A Manufacturing method of micro-fabricated device, as well as corresponding with a through-wafer connection 审中-公开
公开(公告)号：JP2009534819A
公开(公告)日：2009-09-24
申请号：JP2009505817
申请日：2007-03-21
申请人：ローベルトボツシユゲゼルシヤフトミツトベシユレンクテルハフツングRobert Bosch Gmbh
发明人：フェイアンド
IPC分类号： H01L21/3205 , H01L23/52 , H01L29/84
CPC分类号： B81B7/0006 , B81C1/0069 , H01L21/76898
摘要：本発明は、半導体基板を貫通するウェハ貫通接続並びに前記ウェハ貫通接続のための製造方法を記載する。この場合、トレンチエッチングプロセスを用いたウェハ貫通接続の形成のために、半導体基板の前面側内に少なくとも１つのビアホールを作成する。引き続き、前記ビアホールの側壁の前記半導体材料を電気化学的エッチングプロセスで多孔性にエッチングする。前記コンタクトの電気的接続を形成させるために、前記ビアホール中に金属を導入する。半導体基板の前面側から背面側への電気的接続を可能にするために、例えば前記半導体基板を薄くすることにより背面側から前記ビアホールが開口される。前記開口は、この場合、前記ビアホール内への金属の導入の前又は導入の後で行うことができる。

87. 发明专利

JP2008260297A Structure having template provided with nanoscale feature and its manufacturing method 有权
标题翻译：具有纳米特征的模板结构及其制造方法
公开(公告)号：JP2008260297A
公开(公告)日：2008-10-30
申请号：JP2008132877
申请日：2008-05-21
申请人： Hewlett-Packard Development Co Lp , ヒューレット−パッカードデベロップメントカンパニーエル.ピー.
发明人： STASIAK JAMES W , PETERS KEVIN FRANCIS , KORNILOVICH PAVEL
IPC分类号： B29C59/02 , B81C99/00 , B81B7/00 , B82B1/00 , B82B3/00 , C12Q1/68 , G03F7/00 , H01L21/027 , H01L21/768
CPC分类号： G03F7/0002 , B81B7/0006 , B81C1/00126 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C12Q1/68 , H01L21/76817 , H01L21/76877 , H01L2221/1094
摘要： PROBLEM TO BE SOLVED: To provide a nanoscale structure which is manufactured by controlling the number, size, shapes, orientation, patterns and positions of nanoscale objects on a substrate, and to provide its manufacturing method. SOLUTION: In the structure described in a working example of the present invention and its manufacturing method, a template is provided with a resist layer having apertures, in which an assembly is formed by controlling the nanoscale objects. The template is formed for forming patterns having the nanoscale feature that is arranged on the substrate. COPYRIGHT: (C)2009,JPO&INPIT

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