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81. 发明专利

JPH02216869A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02216869A
公开(公告)日：1990-08-29
申请号：JP3616289
申请日：1989-02-17
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , NAGANO TAKAHIRO
IPC分类号： H01L29/78 , H01L29/786
摘要： PURPOSE:To obtain a fine, high speed and high reliability MIS type FET with high electron mobility and without contact problem by making the thickness of a first conduction type semiconductor region less than the thickness of a second semiconductor region. CONSTITUTION:Polysilicon or amorphous silicon is deposited on an insulating substrate 1 in a thickness not less than 100Angstrom , and monocrystallized by laser annealing, etc., and a part to be channel is oxidized by selective oxidation. Then, amorphous silicon is deposited in a thickness of about 500Angstrom and is monocrystallized to form a structure with semiconductor layers of different thicknesses. Then, a p-type impurity is ion-implanted to form a gate oxide film 5 and a gate electrode 6, and an n-type impurity is ion-implanted to form source.drain regions 3, 4, and a passivation film 7 is applied and metal wirings 8 are formed to manufacture an MOSFET.

82. 发明专利

JPH01243589A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01243589A
公开(公告)日：1989-09-28
申请号：JP7105488
申请日：1988-03-25
申请人： HITACHI LTD
发明人： OBAYASHI MASAYUKI , NAGANO TAKAHIRO
IPC分类号： H01L27/04 , H01L21/76 , H01L21/761 , H01L21/762 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/78
摘要： PURPOSE:To reduce an occupation area of a resistance element by employing a high impurity concentration buried layer as the resistance element and forming most part of the high impurity concentration buried layer within a projection region of a MOSFET. CONSTITUTION:A P type semiconductor region 5-1 is formed in an N type semiconductor region 4 by impurity diffusion, constituting a well region of a longitudinal power MOSFET 50. An N type semiconductor region 7 constitut ing a source region. An N type semiconductor region 6 formed on the surface fraction of an N type semiconductor region 3 forms a drain contact region of a longitudinal power MOSFET 50. P type semiconductor regions 9-1, 9-2 formed in the N type semiconductor region 4 constitute a drain region and a source region of a P MOS transistor 18 of a CMOS circuit, respectively. Drain resistance formed in a projection region of the longitudinal power MOSFET 50 is produced owing to the N semiconductor region 3 and the N type semiconductor region 4, whereby an occupation area of electrostatic break down protective element in the semiconductor device can be reduced.

83. 发明专利

JPH01187857A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01187857A
公开(公告)日：1989-07-27
申请号：JP1214588
申请日：1988-01-22
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , WAKUI TAKAYUKI , NAGANO TAKAHIRO
IPC分类号： H01L21/8244 , H01L27/11
摘要： PURPOSE:To obtain the memory cell of a static random access memory having a small memory cell area and a large soft error resistance by burying a conductive substance in a groove and electrically connecting a second conductivity type first semiconductor region to a second conductivity type third semiconductor region. CONSTITUTION:An n type buried layer 12 is connected to the source region 7 of a driver MOSFET by a polycrystalline silicon 1 doped with an N-type impurity. The layer 12 is electrically connected to the source region 7 of the MOSFET by the silicon 1, and a ground potential is supplied from the layer 12 to the region 7 of the MOSFET. Noise charge generated in the layer 12 and a p-type substrate 12 disposed under the layer 12 becomes a barrier so as not to arrive at the drain region 8 of the MOSFET of the information storage region of the memory. Accordingly, a soft error scarcely occurs. Since wirings for supplying the potential to the region 7 is eliminated, the memory cell having small area can be obtained.

84. 发明专利

JPS63289870A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63289870A
公开(公告)日：1988-11-28
申请号：JP12442587
申请日：1987-05-21
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , NAGANO TAKAHIRO
IPC分类号： H01L29/78 , H01L21/76 , H01L29/06 , H01L29/08
摘要： PURPOSE:To prevent a malfunction due to an external noise by a method wherein the bottom of a drain of an MISFET is surrounded by a source which is biased at a definite potential and a substrate is insulated from the drain. CONSTITUTION:An n-type buried layer 9 is formed; it covers the bottom of a drain 4 and a channel formation part under a gate electrode; an n-type extraction region 6 which can reach the n-type buried layer 9 from a source 5 is formed; a source potential is supplied to the n-type buried layer 9; in addition, an n-type region 10 is formed also under a field oxide film 6; the grain 4 and a p-well 7 are separated completely from a p-substrate 1. When a noise electron is generated by an external noise inside the p-substrate 1, the noise electron is diffused inside the p-substrate 1. Because the diffused electron is captured in the source 5, the n-type extraction region 8, the n-type region 10 or the n-type buried layer 9, it does not reach the drain 4. By this setup, it is possible to prevent a malfunction of a circuit due to the external noise.

85. 发明专利

JPS63289862A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63289862A
公开(公告)日：1988-11-28
申请号：JP12442487
申请日：1987-05-21
申请人： HITACHI LTD
发明人： SAWAHATA YASUO , WATANABE TOKUO , NAGANO TAKAHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/72
摘要： PURPOSE:To obtain a high hFE value by a method wherein a region to prevent a carrier from being injected from a first region is installed to be adjacent to one part of a part of the first region excluding the neighborhood facing a third region via a second region. CONSTITUTION:A region to prevent a carrier from being injected from a first region 5, e.g. a region 4 whose conductivity type is the same as that of a second region 5 and whose impurity concentration is higher than that of this region, or an insulator layer is installed to be adjacent to at least one part of a part of the first region 6 excluding the neighborhood facing a third region 9 via the second region 5. Accordingly, regarding the carrier which is injected from the first region (an emitter) to the second region (a base) an amount or a ratio which does not contribute to an electric current of the third region (a collector) is reduced. By this setup, it is possible to enhance an hFE value of a semiconductor device.

86. 发明专利

JPS6358376B2 失效
公开(公告)号：JPS6358376B2
公开(公告)日：1988-11-15
申请号：JP11981080
申请日：1980-09-01
申请人： HITACHI LTD
发明人： YAO TSUTOMU , NAITO MASAMI , NAGANO TAKAHIRO , YASUDA TOMIRO , OONUKI HITOSHI , YANAGI MITSUO , SATO FUMIO
IPC分类号： H01L29/74 , H01L21/52 , H01L23/48 , H01L23/482 , H01L29/08 , H01L29/423 , H01L29/744

87. 发明专利

JPS63254769A VERTICAL INSULATED-GATE TYPE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPS63254769A
公开(公告)日：1988-10-21
申请号：JP8883887
申请日：1987-04-13
申请人： HITACHI LTD
发明人： YAZAWA YOSHIAKI , NAGANO TAKAHIRO
IPC分类号： H01L29/08 , H01L29/423 , H01L29/78
摘要： PURPOSE:To reduce a space between wells without increasing the ON resistance of a vertical double-diffusion MOSFET (VDMOS) and decrease the product (Rons) of the area of an element and the ON resistance, by forming a groove in a semiconductor substrate between neighboring base body regions, and making the concentration of first conductivity type impurities around said groove in the semiconductor substrate higher than that in a drift region. CONSTITUTION:A groove 20 is formed in a region held between wells 13. The concentration of impurities around the groove is made high, and the resistance at this part is decreased. Namely, the impurities, whose concentration is higher than that in another drift region 11, is introduced in a contact part of the groove 20 and the drift region 11. Therefore, even if a depletion layer is expanded toward the drift region 11 from the boundary part between the wells and the drift region, a high concentration impurity layer 21 around the groove is not depleted, and a low resistance state can be kept. Thus the Rons of a VDMOS can be decreased without impairing the breakdown strength of an element and without requiring especially high machining accuracy.

88. 发明专利

JPS63216376A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63216376A
公开(公告)日：1988-09-08
申请号：JP5085587
申请日：1987-03-05
申请人： HITACHI LTD
发明人： TANBA AKIHIRO , YAZAWA YOSHIAKI , WATANABE TOKUO , NAGANO TAKAHIRO , MINAMI MASATAKA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/161 , H01L29/165 , H01L29/72 , H01L29/737
摘要： PURPOSE:To lower the resistance of an emitter without destroying the advantage of increase in the emitter injection efficiency, by causing the emitter to be composed of the first semiconductor where its energy gap is larger than that of the semiconductor to form a base as well as of the second semiconductor where its energy gap is equal to or is smaller than that of the first semiconductor. CONSTITUTION:In the case of a bipolar semiconductor device where an emitter 1, a base 2, and a collector 3 are joined by the use of hetero junction, the emitter 1 is composed of the first semiconductor 4 where its energy gap Eg4 is larger than that Eg2 of the semiconductor to form the base 2 as well as of the second semiconductor where its energy gap is equal to that Eg4 of the first semiconductor 4 at least or smaller than its Eg4. For example, the base 2 and base contact region 5 are formed at a silicon substrate 13 where its substrate allows n-type silicon 12 to act as collector 3 and to perform an epitaxial growth at an n type buried layer 11. After that, an emitter opening part is formed and about 50 Angstrom of an n type a-SiC 7 is formed and then about 1000 Angstrom of n type poly-Si 6 is formed with a plasma CVD technique. The emitter 1 is composed of the element 6 and 7.

89. 发明专利

JPS63215066A LATERAL NPN TRANSISTOR 失效
公开(公告)号：JPS63215066A
公开(公告)日：1988-09-07
申请号：JP4757187
申请日：1987-03-04
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , NAGANO TAKAHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/10
摘要： PURPOSE:To obtain a highly precise base width which is not limited by the minimum working measurements by a method wherein emitter and base impurities are introduced in lateral direction from the same surface of the stepping- formed side wall of the groove part provided on a semiconductor substrate. CONSTITUTION:A groove of about 0.1 mum-several mum in depth and several-ten-odd mum or thereabout in width is formed by etching on a P-type semiconductor substrate 1, and a part of the groove and a part of its edge are covered by a film which is hardly oxidized. Then, LOCOS 3a and 3b are formed by performing a local oxidizing process, and an N-type collector region 2 is formed by introducing N-type impurities from above. Subsequently, an N -layer 7 and a P -type layer 8 are provided by introducing impurities into the region 2. Then, a base 5 and an emitter 4 are formed by introducing P-type and N-type impurities successively into the stepped part on the surface of the substrate.

90. 发明专利

JPS63211671A TRANSVERSE PNP TRANSISTOR 失效
公开(公告)号：JPS63211671A
公开(公告)日：1988-09-02
申请号：JP4263587
申请日：1987-02-27
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , NAGANO TAKAHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/72
摘要： PURPOSE:To improve the rapid operating properties of a PNP transistor, by diffusing dopants for a base and an emitter from the same surface for forming a base width. CONSTITUTION:A base width is formed by introducing dopants of an emitter 4 and a base 5 transversely from the side walls of steps provided on a semiconductor substrate 1. Thus, the dopants are introduced through a mask of photoresist or the like, so that an N layer 8, a P layer 7 and a P layer 6 are provided. A material having desirable resistance to oxidation is deposited on the whole surface and then anisotropically etched so as to leave the sidewalls 13 on the steps on the substrate surface. Thermal oxidation is carried out for providing an oxide film having a thickness of about 0.1-0.3 mum on the region except the sidewalls. The sidewalls are then removed by means of phosphoric acid or the like. Through the aperture formed thereby, N-type and P-type dopants are successively introduced so as to form the base 5 and the emitter 6, respectively. In this manner, a PNP transistor capable of operating at a high speed can be obtained.

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