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71. 发明专利

JPH11513218A 失效
公开(公告)号：JPH11513218A
公开(公告)日：1999-11-09
申请号：JP50488598
申请日：1997-07-10
IPC分类号： H04L7/033 , H04L7/027

72. 发明专利

JP2949647B2 失效
公开(公告)号：JP2949647B2
公开(公告)日：1999-09-20
申请号：JP50852991
申请日：1991-05-08
申请人： BURITEITSUSHU TEREKOMYUNIKEESHONZU PLC
发明人： UETSUBU RODERITSUKU PIITAA
IPC分类号： G02F3/02 , G02F2/00 , G02F3/00 , H01S3/06 , H01S3/094 , H01S3/10 , H01S5/00 , H01S5/50 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/142 , H04B10/152 , H04B10/26 , H04B10/43 , H04L7/00 , H04L7/027 , H01S3/18 , H04B10/28

73. 发明专利

JP2929925B2 失效
公开(公告)号：JP2929925B2
公开(公告)日：1999-08-03
申请号：JP33426093
申请日：1993-12-28
申请人： NIPPON DENKI KK
发明人： KANAI KAZUNAGA
IPC分类号： H04L27/22 , H04L7/027

74. 发明专利

JPH11196075A BIT SYNCHRONOUS CIRCUIT 失效
公开(公告)号：JPH11196075A
公开(公告)日：1999-07-21
申请号：JP36669597
申请日：1997-12-26
申请人： CASIO COMPUTER CO LTD
发明人： IMAMURA TAKESHI
IPC分类号： H03L7/00 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide a bit synchronous circuit, which has a fast synchronous converging operation, high stability and an improved degrees of freedom of a circuit despite its reduced scale by preparing a limit means, which subtracts the held value of a holding means from the count value of a counter and limits this difference output at a fixed rate and then adding the output of the limit means to the held value of the holding means to give this sum output to the holding means. SOLUTION: This circuit includes an edge detection means 21, which detects the edge position of a binary signal to be inputted, an N-notation counter 25 which counts the clocks having frequency of N times as high as the binary signal (N=2, 3...) and a holding means 22 which holds the sum output of an adder 23, in response to the detection timing of the means 21. A subtraction means 24 subtracts the held value of the means 22 from the count value of the counter 25 and outputs the difference output as a synchronizing signal of the binary signal. The adder 23 limits the difference output of the means 24 at a fixed rate and then adds the output of a limit means 26 to the held value of the means 22 to give this sum output to the means 22.

75. 发明专利

JPH11127143A CLOCK SIGNAL RECOVERY DEVICE 失效
公开(公告)号：JPH11127143A
公开(公告)日：1999-05-11
申请号：JP29143797
申请日：1997-10-23
申请人： NEC CORP
发明人： NODA ARIHIDE
IPC分类号： H04B10/556 , H04B10/00 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To improve the extract efficiency of a clock signal without complicating the configuration of a circuit for recovering the clock signal. SOLUTION: A signal whose transmission speed is one over an even number in a reception equalization signal is extracted through an extract filter 21 and a broadband amplifier 22 and a frequency multiplier circuit 23 multiplies the signal by a multiple of even numbers. The multiplied resulting signal whose transmission speed is equal to that of the received signal is given to a timing filter (dielectric resonator) 24 having a band-pass characteristic whose Q is enhanced by sufficiently narrowing the pass-band width, and a clock signal is extracted. The clock signal is given to a limiter amplifier 25, where the signal is amplified into a rectangular wave signal to obtain a recovered clock signal.

76. 发明专利

JPH11122230A SYNCHRONIZING METHOD FOR DATA COMMUNICATION SYSTEM AND DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPH11122230A
公开(公告)日：1999-04-30
申请号：JP28653297
申请日：1997-10-20
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： G06F1/08 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To eliminate the need of adding a synchronizing signal to all response signals and to improve the efficiency of communication between transmission/ reception by permitting a transmission side to transmit transmission data in accordance with an inner reference signal, and permitting a reception side to generate a clock based on a transmission signal and to send the response signal to the transmission side in synchronizing with the clock. SOLUTION: A PLL circuit 8 phase-synchronizes the output clock with a reception signal. A shaping circuit 11 samples the reception signal at a sample clock and holds the value. When a SYNC circuit 10 receives the prescribed quantity of received bit strings matched with a synchronizing signal pattern, the PLL circuit 8 is locked and the output of the matching circuit 11 is written in a memory 9 in synchronizing with a bit clock Bitclk'. At the time of returning the response signal after reception terminates, the response signal is transmitted in synchronizing with the bit clock Bitclk'. On the other hand, the transmission side samples the response signal in accordance with the reception timing of the response signal.

77. 发明专利

JP2885494B2 失效
公开(公告)号：JP2885494B2
公开(公告)日：1999-04-26
申请号：JP22083190
申请日：1990-08-21
申请人： NIPPON DENKI KK , NIPPON DENSHIN DENWA KK , ENU TEI TEI IDO TSUSHINMO KK
发明人： TAKAHASHI BUNJI , YAMANE HIROAKI
IPC分类号： H04L25/02 , H04L7/027

78. 发明专利

JPH11504425A 失效
公开(公告)号：JPH11504425A
公开(公告)日：1999-04-20
申请号：JP53228296
申请日：1996-04-26
IPC分类号： G01S13/74 , G01R25/00 , G01S13/75 , G01S13/78 , G06K7/00 , G06K7/08 , H03D13/00 , H04B1/59 , H04B5/02 , H04L7/027 , H04L7/033

79. 发明专利

JP2847298B2 失效
公开(公告)号：JP2847298B2
公开(公告)日：1999-01-13
申请号：JP22188289
申请日：1989-08-30
申请人： JIIMENSU AG
发明人： HAINRITSUHI SHENKU
IPC分类号： H04L7/027 , H03L7/093 , H03L7/107 , H04L7/02 , H04L7/033

80. 发明专利

JPH10290179A PREDISTORTION CIRCUIT FOR RADIO FREQUENCY AMPLIFIER 失效
公开(公告)号：JPH10290179A
公开(公告)日：1998-10-27
申请号：JP11021098
申请日：1998-04-06
申请人： HARRIS CORP
发明人： DANIELSONS DAVID
IPC分类号： H04B1/62 , G11B20/18 , H01Q5/364 , H01Q5/50 , H01Q21/26 , H01Q21/30 , H03L7/185 , H03M13/15 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H04J3/06 , H04L1/00 , H04L5/00 , H04L7/00 , H04L7/027 , H04L7/08 , H04L27/00 , H04L27/34 , H04L27/36 , H04N1/00 , H04N5/04 , H04N5/08 , H04N5/14 , H04N5/21 , H04N5/38 , H04N5/44 , H04N7/08 , H04N7/081 , H04N7/24 , H04N7/26 , H04N7/66 , H04N11/00 , H04N11/24 , H04N19/89 , H04N21/2383 , H04N21/2385 , H04N21/242 , H04N21/431 , H04N21/438 , H04N21/6379
摘要： PROBLEM TO BE SOLVED: To cancel all the unwanted distortion of radio frequency(RF) amplifier by providing a linearity and phase corrector, with which predistortion is applied to a signal to be supplied to the RF amplifier, and inserting this frequency response and phase corrector between the linearity corrector and the amplifier. SOLUTION: By adjusting the non-linearity and target frequency of specified amplifier 170 through a linearity corrector 164 and a phase corrector 162 which are adjusted so as to invert the amplitude and phase response of non-linear amplifier, the phase corrector 162 prevents the precorrecting adjustment of amplitude from exerting any adverse influence upon the precorrection of phase while being provided on the upper step of linearity corrector 164. Then, a frequency response corrector 166 is provided between the linearity corrector 164 and amplitude input circuit 168 so as to compensate an input signal. Since an amplifier output circuit 172 changes the frequency and phase response of entire system sometimes, by providing a frequency response corrector 160, the frequency response and phase response of entire system are corrected transparent.

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