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1. 发明专利

JP2001257624A SPREAD SPECTRUM COMMUNICATION UNIT 失效
公开(公告)号：JP2001257624A
公开(公告)日：2001-09-21
申请号：JP2001071348
申请日：2001-03-14
申请人： PFU LTD
发明人： SHIMADA TETSUYA , MORIFUJI TOSHIAKI , ARAI MASAKI , KOTANI MAKOTO
IPC分类号： H04B1/707 , H04B1/7085 , H04B1/709
摘要： PROBLEM TO BE SOLVED: To provide a spread spectrum communication unit adopting a simple circuit configuration, which can accurately generate demodulation data. SOLUTION: The spread spectrum communication unit is provided with a generating means that generates a spread spectrum code and a correlation means that detects the correlation between a spread spectrum code of a received signal and a spread spectrum code generated from the generating means and generates two correlation coincidence signals for one period of the spread spectrum code when detecting the correlation coincidence, and with a vanish means that vanishes a specified correlation coincidence signal of the two correlation coincidence signals when adopting a configuration of demodulating the received signal that is subjected to spread spectrum processing by using the correlation coincidence signals, a counter means that counts the number of clock signals by using the correlation coincidence signal not vanished for a reset signal, and a gate means that inhibits input of the clock signal to the count means when the count of the counter means reaches a specified count. Thus, demodulation data are generated from an output terminal of the counter means.

2. 发明专利

JPH11215100A SPREAD SPECTRUM COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH11215100A
公开(公告)日：1999-08-06
申请号：JP935498
申请日：1998-01-21
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： H04J13/00 , H04B1/7093 , H04L7/00 , H04J13/04
摘要： PROBLEM TO BE SOLVED: To provide a spread spectrum communication equipment which stably obtain a correlation output of level by performing sending data processing suitably. SOLUTION: This spread spectrum communication device, where a transmitter side sends a multiplex modulation signal by shifting a multiplexing timing and a receiver side gets demodulation data from a correlation output, is provided with a delay quantity deciding means 10, which decides change quantity of multiplexing timing on the transmitter side for each combination of sending data and a correlation output processing means 20 which compares a correlation output, only in a timing in which a correlation output is supposed to be outputted.

3. 发明专利

JP2011193349A Antenna built-in image pickup device 有权
标题翻译：天线内置图像拾取器件
公开(公告)号：JP2011193349A
公开(公告)日：2011-09-29
申请号：JP2010059345
申请日：2010-03-16
申请人： Pfu Ltd , 株式会社Pfu
发明人： MORIFUJI TOSHIAKI
IPC分类号： H01Q1/24 , G06K17/00
摘要： PROBLEM TO BE SOLVED: To provide an antenna built-in image pickup device that strikes a balance between non-contact communication with a storage medium and clear picked-up image thereof. SOLUTION: A thin scanner 1 that is the antenna built-in image pickup device includes: an image read portion 10 for reading an image of a NFC card 100; a metal case body 7 for holding the image read portion 10; an antenna pattern 41 for carrying out communication with the NFC card 100; a NFC antenna 40 which covers the entire surface of the image read portion 10 on a side opposite to a surface of a side for reading the image of the NFC card 100 in the image read portion 10 and which is disposed in the case body 7; and a magnetic sheet 50 with magnetic force, which covers the entire surface of the image read portion 10 on a side opposite to a surface of a side of the image read portion 10 in the NFC antenna 40 and which is disposed in the case body 7. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种天线内置图像拾取装置，其在与存储介质的非接触通信和其清除的拾取图像之间达到平衡。天线内置图像拾取装置的薄扫描器1包括：用于读取NFC卡100的图像的图像读取部分10; 用于保持图像读取部分10的金属外壳本体7; 用于与NFC卡100进行通信的天线图案41; NFC天线40，其覆盖图像读取部分10的与用于读取图像读取部分10中的NFC卡100的图像的一侧的表面相反的一侧的整个表面，并且设置在盒体7中; 以及具有磁力的磁片50，其覆盖图像读取部10的与NFC天线40中的图像读取部10的一侧的表面相对的一侧的整个表面，并且设置在壳体7中版权所有（C）2011，JPO＆INPIT

4. 发明专利

JPH06161703A MULTI-DISPLAY DEVICE AND METHOD FOR FITTING FLAT PLATE TYPE DISPLAY 失效
公开(公告)号：JPH06161703A
公开(公告)日：1994-06-10
申请号：JP33533892
申请日：1992-11-20
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI , SHIMADA TETSUYA , ARAI MASAKI , SHUKUTANI TOSHIRO , WATANABE MASAKI , UESUGI SHIGENORI
IPC分类号： G06F1/16 , G06F1/18 , G06F3/048 , G06F3/14 , G06F3/153 , G09F9/00
摘要： PURPOSE:To provide the multi-display device whose display screen can be seen by a person other than an operator. CONSTITUTION:A character 'B' is displayed on a 1st flat plate type display and a character 'A' is displayed on a 2nd flat plate type display. When the 2nd flat plate type display is fallen to the back side and the character 'A' is inverted. So that the character and a picture on the 2nd flat plate type display can be seen in an erect state, a sensor detects the angle between the 1st flat plate type display and 2nd flat plate type display and if the display is fallen to the back side, pixel data D0, D1...Dn are written in addresses (n), (n-1)...0, but when the display is not fallen to the back side, on the other hand, the pixel data D0, D1...Dn are written in the addresses 0, 1...(n). Read addresses are generated in the order of 0, 1...(n).

5. 发明专利

JPH01116773A PICTURE PROCESSING SYSTEM 失效
公开(公告)号：JPH01116773A
公开(公告)日：1989-05-09
申请号：JP27497687
申请日：1987-10-30
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： G06T11/20
摘要： PURPOSE:To correctly execute drawing and to normally execute a paint processing by comparing and inspecting a plotting address generated by a CRT controller having a plotting function to execute plotting. CONSTITUTION:The plotting address generated by the CRT controller 12 which is not actually plotted is held in a second memory means 14 by invalidating the output of an AND circuit 15 by an external control signal and the plotting address of the memory means 14 is read as required to inspect the plotting address in a host processor 11. It is discriminated whether or not the plotting address can be correctly plotted according to the inspection to output the plotting address again from the CRT controller 12 to a first memory means 13 to be plotted. Accordingly, the plotting can be correctly executed and the paint processing can be normally carried out.

6. 发明专利

JPH11225145A RADIO LAN 失效
公开(公告)号：JPH11225145A
公开(公告)日：1999-08-17
申请号：JP2680998
申请日：1998-02-09
申请人： PFU LTD
发明人： ARAI MASAKI , MORIFUJI TOSHIAKI , KOTANI MAKOTO
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To improve communication efficiency by preventing interference to another cell terminal. SOLUTION: The radio LAN consists of pluralities of servers, pluralities of terminals 20 provided corresponding to each of pluralities of the servers and making radio transmission by a radio channel with a corresponding server provided to a range (cell) within the reach of the radio wave outputted form the corresponding server. Each terminal 20 is provided with a transmission control means 40 that decides a transmission signal based on an RSSI signal and a correlation output. Each terminal 20 makes transmission to the corresponding server with a transmission output decided by the transmission control means 40 provided to each.

7. 发明专利

JPH11122230A SYNCHRONIZING METHOD FOR DATA COMMUNICATION SYSTEM AND DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPH11122230A
公开(公告)日：1999-04-30
申请号：JP28653297
申请日：1997-10-20
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： G06F1/08 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To eliminate the need of adding a synchronizing signal to all response signals and to improve the efficiency of communication between transmission/ reception by permitting a transmission side to transmit transmission data in accordance with an inner reference signal, and permitting a reception side to generate a clock based on a transmission signal and to send the response signal to the transmission side in synchronizing with the clock. SOLUTION: A PLL circuit 8 phase-synchronizes the output clock with a reception signal. A shaping circuit 11 samples the reception signal at a sample clock and holds the value. When a SYNC circuit 10 receives the prescribed quantity of received bit strings matched with a synchronizing signal pattern, the PLL circuit 8 is locked and the output of the matching circuit 11 is written in a memory 9 in synchronizing with a bit clock Bitclk'. At the time of returning the response signal after reception terminates, the response signal is transmitted in synchronizing with the bit clock Bitclk'. On the other hand, the transmission side samples the response signal in accordance with the reception timing of the response signal.

8. 发明专利

JPH1041832A INTERLEAVE PROCESSOR FOR DATA COMMUNICATION 失效
公开(公告)号：JPH1041832A
公开(公告)日：1998-02-13
申请号：JP19793696
申请日：1996-07-26
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： H03M13/27 , H03M13/22
摘要： PROBLEM TO BE SOLVED: To decrease overhead which is caused by interleave and to reduce the capacitance of a memory by synchronizing the timing for the processing of write and decode on the receiving side. SOLUTION: This device is provided with a clock-generating means 1 for receiving to generate a clock for decoding and a bit clock and an address timing-generating means 2 for transmitting the instruction for the order of write addresses to a storage part 106 for interleave at a receiver, the instruction for the order of read addresses from the storage part 106, and a decode start signal to a decoder 107. Then, the timing for writing, reading and decoding of the received data into the storage part 106 on the receiver side is synchronized. Thus, data can be completely received and completely decoded almost simultaneously on the receiving side, overhead can be reduced, and communication efficiency can be improved.

9. 发明专利

JPH07202851A RADIO COMMUNICATION SYSTEM 失效
公开(公告)号：JPH07202851A
公开(公告)日：1995-08-04
申请号：JP33741193
申请日：1993-12-28
申请人： PFU LTD
发明人： MORIFUJI TOSHIAKI
IPC分类号： H04L1/00 , H03M13/27 , H04B14/04 , H03M13/22
摘要： PURPOSE:To allow the receiver side to make relevant decoding even when a transmitter side varies an interleave size by decoding a frame with the interleave size in a shortest hamming distance for received frames. CONSTITUTION:A receiver side receives one frame of interleaved data by a transmitter side. An address control section 3 reads data received from a memory 2 as to each interleave size under the control of a size dependent hamming distance calculation section 4 of an automatic discrimination section 1 to calculate a hamming distance corresponding to each size. The calculation section 4 makes decoding including data error correction from the memory 2 based on a designated interleave size and compares the decoded data with the read data. Then a bit number (hamming distance) different from bits is outputted to an interleave size discrimination section 5. The discrimination section 5 discriminates the minimum interleave size and outputs the result to a decoding section 6 before end of one frame and the data are read from the memory 6a according to the size and the read data are decoded.

10. 发明专利

JPH075819A CONNECTING METHOD FOR FLAT PLANE DISPLAY 失效
公开(公告)号：JPH075819A
公开(公告)日：1995-01-10
申请号：JP36139492
申请日：1992-12-29
申请人： PFU LTD
发明人： WATANABE MASAKI , UESUGI SHIGENORI , SHIMADA TETSUYA , ARAI MASAKI , SHUKUTANI TOSHIRO , MORIFUJI TOSHIAKI
IPC分类号： G09F9/00 , H01R4/60
摘要： PURPOSE:To make it possible to freely mountably/dismountably connecting a separate flat plane display to a flat plane display so that the same or different images are displayed on each of the plural flat plane displays. CONSTITUTION:A plug 10 is connected to the sub-display and a socket 20 to the main display. The socket 20 is rotatable in a direction (2). The plug 10 is rotatable in a direction (1). The plug 10 has an outer electrode 11, an inner electrode 12, an electric insulating layer 13 and a light receiving body 14. A data line is connected to this light receiving body 14. The socket 20 has an electrode 21 connected to the outer electrode 11, an electrode 22 connected to the inner electrode 12 and a light emitting body 24 facing the light receiving body 14. A data line is connected to the light emitting body 24. Electric power and data are transmitted from the main display to the sub-display when the plug 10 is inserted into the socket 20.

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