专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明专利

JP3146308B2 失效
公开(公告)号：JP3146308B2
公开(公告)日：2001-03-12
申请号：JP22144190
申请日：1990-08-24
IPC分类号： G06F7/38 , G06F5/00 , G06F7/00 , G06F7/485 , G06F7/487 , G06F7/76 , G06F7/78 , G06F17/16 , G06T9/00 , G06F7/50

72. 发明专利

JP2001034456A EQUALIZE CIRCUIT 失效
公开(公告)号：JP2001034456A
公开(公告)日：2001-02-09
申请号：JP20844999
申请日：1999-07-23
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F7/485 , G06F7/50
摘要： PROBLEM TO BE SOLVED: To provide an equalize circuit realizing high speed performance by reducing the number of steps of an arithmetic circuit for performing the addition/subtraction of floating point data. SOLUTION: This circuit is provided with a memory means which stores data A and data B indicating two numbers, a logical circuit 4 for detecting the number of equalize shift which judges the size of exponent part data Ae of data A and exponent data Be of data B, and detects the number of equalize shift being a difference between the exponent data Ae and Be, and outputs those results, an equalize shift circuit which operates the arithmetic shift of mantissa part data Bm corresponding to the smaller exponent data Be based on the result of the size judgment by the number of equalize shift, and outputs the arithmetic result as processed data Beq, and outputs mantissa part data Am corresponding to the larger exponent data Ae as processed data Aeq, and an arithmetic means which executes addition/subtraction to the processed data Aeq and the processed data Beq.

75. 发明专利

JP2000347834A ARITHMETIC CIRCUIT BY SW NUMBER SYSTEM 失效
公开(公告)号：JP2000347834A
公开(公告)日：2000-12-15
申请号：JP16173199
申请日：1999-06-08
申请人： JAPAN SCIENCE & TECH CORP
发明人： AOKI TAKAFUMI , HIGUCHI TATSUO , SAWADA YOSHIKI
IPC分类号： G06F7/505 , G06F7/50 , H03H17/02 , H03H17/06
摘要： PROBLEM TO BE SOLVED: To completely make an addition algorithm into module without using irregular operation by freely setting the codes of respective digits determined by code vectors in the respective steps of arithmetic. SOLUTION: The architecture of a settable cellular array 500 is composed of a settable arithmetic block (CAB), a connection block(CB) and a switch block(SB). When a digital filter is composed of the settable cellular array 500, an input signal is inputted to the digital filter by an A/D converter 510. This digital signal is converted with a number system used inside this settable cellular array 500 in the first settable arithmetic block (CAB). The digital signal outputted from the cellular array 500 is converted to an ordinary binary number by an output code vector converter 520, made into analog signal by a D/A converter 530 and outputted.

79. 发明专利

JP2000242469A CORRECTED MAIN AND BRANCH TYPE BINARY ADDER 失效
公开(公告)号：JP2000242469A
公开(公告)日：2000-09-08
申请号：JP15693099
申请日：1999-04-26
申请人： SUGIMURA YUKICHI
发明人： SUGIMURA YUKICHI
IPC分类号： G06F7/50 , G06F7/508
摘要： PROBLEM TO BE SOLVED: To produce a binary adder with 3.75 gates. SOLUTION: All digits are divided into branch lines (b) of (n) digits (n=2 to 3) and following main lines (m), H signals on all the digits after (m) digits are inputted to the (m) lines, a transistor tr is turned off by turning a base be of tr to H, an emitter (e) is turned to H, the higher (b) lines are turned to H by Vcc, 00 signals from (digits of b lines)-1) digits to (m) digits are inputted to (b) lines, private lines p1 and p2, etc., are provided for the case of lower digit 00 and upper digit 11 on (b) lines and H signals on digits inputted to (m) lines are changed from H to L by subtracting them with 00 and L signals of higher digits. The number of gates is 3.75, there is an adding speed 2.93 times as high as a binary look-ahead adder composed of 64 digits and 11 steps and the number of gates is 1/2.07.

80. 发明专利

JP2000222175A IMPROVED OPTOELECTRONIC TWO-STAGE 11 AND 00 CUT ADDER 失效
公开(公告)号：JP2000222175A
公开(公告)日：2000-08-11
申请号：JP32278698
申请日：1998-10-07
申请人： SUGIMURA YUKICHI
发明人： SUGIMURA YUKICHI
IPC分类号： G06E1/00 , G06F7/50 , G06F7/508
摘要： PROBLEM TO BE SOLVED: To improve an addition speed by using AND gates by digits to be sent although conventional technology uses one AND gate for a carry signal sent from a certain start-point-(s) digit to several end-point-(t) digits. SOLUTION: The AND(1)H output (high voltages) carry signal C of a start- point-(s) digit is inputted to the base be(4) of a transistor tr(3) through a Cts line (2) and further connected to H (high voltage) through a resistance (5), and the laser diodes LD and Uc(6) or an end-point-(t) digit is connected to a collector of the tr. When it is (s)-digit AB=11, and AND (1) outputs H, when be(4) is H, the tr turns on to make the Uc illuminate. The 11 of intermediate (S+1) to (t-1) digits, 00 generated by OR(7) and an L signal (0 voltage), however, are inputted to the Cts line (2) through a downward diode di(8), so when there is even one 00 halfway, be(4) becomes L and the tr turns off, so that Uc goes out.

你已经成功收藏专利！

检索式保存成功!

IPRDB