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1. 发明专利

JPH10161854A FAST DIVISION CIRCUIT 失效
公开(公告)号：JPH10161854A
公开(公告)日：1998-06-19
申请号：JP32386496
申请日：1996-12-04
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535
摘要： PROBLEM TO BE SOLVED: To provide a division circuit which can increase the computing speed of one-processing cycle of division. SOLUTION: An arithmetic mode decision circuit 3 is added to a division circuit 4 of a conventional nonrestoring division system. The circuit 3 generates the arithmetic mode data to designate the addition or the subtraction that should be executed by an addition/subtraction part 2 based on the code bit of the dividend data or the remainder data and the code bit of the divisor data. Then the arithmetic mode data are supplied to part 2 before the part 2 inputs the dividend data or the remainder data and the divisor data via a data bus. Thus, the time needed for the part 2 to decide the addition or subtraction can be omitted and accordingly the division time is shortened.

2. 发明专利

JPH07146778A FLOATING POINT ADDER-SUBTRACTER 失效
公开(公告)号：JPH07146778A
公开(公告)日：1995-06-06
申请号：JP31609593
申请日：1993-11-22
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/485 , G06F7/50 , G06F7/76
摘要： PURPOSE:To provide a floating point adder-subtracter which is capable of performing a calculation at high speed by performing the normalization processing by a hardware when an overflow is generated, related to a floating point adder-subtracter performing the addition/subtraction of mantissa part data. CONSTITUTION:An arithmetic unit 2 performs the addition and subtraction of mantissa part data S2 and S3 from register file 1. The arithmetic result data S5 obtained by this addition and subtraction is stored in the register 1 and an overflow bit S1 is stored in a register 4. When the output of an overflow bit S1 is inputted from the register 4, a barrel shifter 3 unconditionally shifts input mantissa part data S4 (arithmetic result data S5 before a normalization processing) by 1-bit in the right direction, synthesizes the logical invertion data of the most significant bit of the input mantissa part data with the most significant bit where a free area is produced by the shift and outputs this synthesized data as a mantissa part data S6 for which the normalization processing is performed.

3. 发明专利

JP2001331340A SYSTEM AND METHOD FOR SWITCHING MODE BY CODE CHECKING 失效
公开(公告)号：JP2001331340A
公开(公告)日：2001-11-30
申请号：JP2000147657
申请日：2000-05-19
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F11/22 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To prevent the internal information of a microprocessor chip, having a function for switching a user mode and a test mode and including a built-in ROM from being leaked by preventing a user mode operation state from being switched easily to a test mode operation state, when it is necessary to switch the chip to the test mode operation state. SOLUTION: A device 100 is provided with: the microprocessor chip 1 having a CPU 11, a bus 2, a test mode setting terminal 13, and an internal ROM 12 holding a code check program 122 including one or a plurality of address information and code information; and a memory 3 having a check code 31. When the terminal 13 is set up to the test mode, the CPU 11 executes the program 122, reads the check code 31 in the memory 3 by using the address information as the address of the memory 3, and compares the read code 31 with the code information, and if the code 31 matches with the code information, sets up the chip to the test mode operation state.

4. 发明专利

JPH05189206A FLOATING POINT ADDER-SUBSTRACTER 失效
公开(公告)号：JPH05189206A
公开(公告)日：1993-07-30
申请号：JP2457692
申请日：1992-01-14
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F7/485 , G06F7/50 , G06F7/507
摘要： PURPOSE:To speed up an operation by quickly obtaining an equalizing data selection signal at the time of executing addition and subtraction in a floating point adder-subtracter which adds and subtracts floating point data of a system making an exponential part and a matissa part zero and expressing zero. CONSTITUTION:A case when a carry signal S4 outputted from a subtracter 31 subtracting (S1-S2) from exponential part data S1 and S2 of two pieces of floating point data which are added and subtracted becomes zero and a case when it becomes one are assumed. The equalizing data selection signals S10 and S11 in the respective cases are previously generated in computing elements 35 and 36. When the actual carry signal S4 is outputted from the subtracter 31, either the equalizing data selection signal S10 or S11 is selected in a selector 7, and it is added to an equalizer 9 as an equalizing data selection signal S12.

5. 发明专利

JPH04274549A MEMORY CIRCUIT 失效
公开(公告)号：JPH04274549A
公开(公告)日：1992-09-30
申请号：JP5777891
申请日：1991-02-28
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To guarantee the consistency of random access memories in memory circuits provided in corresponding to each processor in a decentralized processing system. CONSTITUTION:When a processor 9 rewrites the content of a random access memory 1, memory rewrite information indicating the rewritten content is transmitted to memory circuits corresponding to other processors constituting a decentralized processing system. Upon receiving the memory rewrite information from a memory circuit 100, the other memory circuits rewrite the contents of the random access memories of their own circuits and, at the same time, transmit echo back information indicating the contents of the rewritten parts to the memory circuit 100. When a reception circuit 6 receives the echo back information, a data retransmission control circuit 12 in the circuit 100 compares the received echo back information with the memory rewrite information sent to the other memory circuits and, when both information do not coincide with each other, retransmits the memory rewrite information.

6. 发明专利

JP2014238749A 粒度の異なるモデルが混在するシミュレーション実行方法审中-公开
标题翻译：具有不同粒子尺寸的模型的模拟执行方法混合
公开(公告)号：JP2014238749A
公开(公告)日：2014-12-18
申请号：JP2013121566
申请日：2013-06-10
申请人：日本電気株式会社 , Nec Corp
发明人： AKAGAWA NAO , ADACHI RYUZO
IPC分类号： G06F19/00 , G06Q10/06
摘要：【課題】シミュレーション対象が広範囲なシミュレーションシステムにおいて、一部のモデルに関して詳細な模擬の要求がある場合、シミュレーションの対象範囲を狭めることなく、進行速度をできるだけ低下させないようにするシミュレーション実行方法が必要となる。【解決手段】第1の粒度のフェデレーションと、第2の粒度のフェデレーションと、ひとつ以上のフェデレートとを有し、前記フェデレートは各々前記第1の粒度のモデルを生成し、前記フェデレートの少なくともひとつはさらに前記第2の粒度のモデルを生成し、前記第1の粒度のモデルは前記第1の粒度のフェデレーションで、前記第2の粒度のモデルは前記第2の粒度のフェデレーションで、シミュレーションを行い、前記第1のモデルと前記第2のモデルとは情報の整合を取りながら前記シミュレーションを行う、シミュレーション実行方法である。【選択図】図1
摘要翻译：要解决的问题：为了提供一种模拟执行方法，以防止在对模拟系统中的一部分模型请求详细模拟时尽可能多地减小提前速度而不使模拟的对象范围变窄，模拟对象范围很宽。解决方案：模拟执行方法包括第一粒度的联合，第二粒度的联合以及一个或多个联合。每个联盟产生第一粒度的模型，并且至少一个联盟生成第二粒度的模型，并且第一粒子的模型通过第一粒子的联合和第二粒子的模型进行模拟粒度通过第二粒径的联合进行模拟，第一模型和第二模型在匹配信息的同时执行模拟。

7. 发明专利

JP2001034456A EQUALIZE CIRCUIT 失效
公开(公告)号：JP2001034456A
公开(公告)日：2001-02-09
申请号：JP20844999
申请日：1999-07-23
申请人： NEC CORP
发明人： ADACHI RYUZO
IPC分类号： G06F7/485 , G06F7/50
摘要： PROBLEM TO BE SOLVED: To provide an equalize circuit realizing high speed performance by reducing the number of steps of an arithmetic circuit for performing the addition/subtraction of floating point data. SOLUTION: This circuit is provided with a memory means which stores data A and data B indicating two numbers, a logical circuit 4 for detecting the number of equalize shift which judges the size of exponent part data Ae of data A and exponent data Be of data B, and detects the number of equalize shift being a difference between the exponent data Ae and Be, and outputs those results, an equalize shift circuit which operates the arithmetic shift of mantissa part data Bm corresponding to the smaller exponent data Be based on the result of the size judgment by the number of equalize shift, and outputs the arithmetic result as processed data Beq, and outputs mantissa part data Am corresponding to the larger exponent data Ae as processed data Aeq, and an arithmetic means which executes addition/subtraction to the processed data Aeq and the processed data Beq.

8. 发明专利

JPH04255433A BATTERY CHARGING CIRCUIT AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04255433A
公开(公告)日：1992-09-10
申请号：JP1407591
申请日：1991-02-05
申请人： NEC CORP
发明人： MURAKAMI SATOSHI , ADACHI RYUZO
IPC分类号： H02J7/34
摘要： PURPOSE:To perform charging optimal to the remaining capacity of battery by providing a battery voltage detector, an ambient temperature detector, and a battery charging current controller for feeding the battery with a variable charging current. CONSTITUTION:Under a state where a power supply 2 is turned ON, a CPU 9 receives the terminal voltage of a battery 6 from a battery voltage detector 5 and an ambient temperature from a temperature detector 7 through an A/D converter 8. The CPU decides the residual capacity of the battery based on the relationship between the ambient temperature and the discharge voltage. Furthermore, the CPU 9 delivers a command for increasing or decreasing the charging current to a battery charging current controller 4 in order to keep the charging rate at a predetermined level. According to the invention, charging operation optimal for the residual capacity of the battery can be carried out.

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