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71. 发明专利

JP2002271213A FM TRANSMITTER 失效
公开(公告)号：JP2002271213A
公开(公告)日：2002-09-20
申请号：JP2001071641
申请日：2001-03-14
申请人： HITACHI LTD
发明人： KOKUBO MASARU
IPC分类号： H03L7/093 , H04B1/04
摘要： PROBLEM TO BE SOLVED: To provide an FM transmitter, in which start/stop can be controlled including a buffer circuit and a sample-and-hold circuit is not required for use in the transition from a PLL to an open loop. SOLUTION: The transmitter is constructed, in such a manner that a control circuit 14 for controlling a charge pump 5 in the PLL to start/stop an FM operation is controlled by using a closed/open loop selection signal CL/OP in the PLL, a start/stop signal PA- PD in a buffer amplifier 9 and a preamble detection signal. Accordingly, since start/stoppage control can be performed so that the buffer amplifier and the PLL in the FM transmitter are controlled jointly, power consumption is reduced.

72. 发明专利

JP2001326574A PHASE SYNCHRONIZATION CIRCUIT AND CLOCK GENERATION CIRCUIT 失效
公开(公告)号：JP2001326574A
公开(公告)日：2001-11-22
申请号：JP2000148580
申请日：2000-05-16
申请人： HITACHI LTD
发明人： SHIBAHARA YOSHIYUKI , KOKUBO MASARU , AOKI HIROKAZU
IPC分类号： H03L7/093 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a phase synchronization circuit and a clock generation circuit capable of keeping stability even in the case of low precision like a resistance element constituting an IC circuit. SOLUTION: The phase synchronization circuit consists of a phase comparator 1, a bias current supplying circuit 2, a charge pump 3, a loop filter 4, a voltage/ current converter 5, a current control oscillator 6 and a frequency divider 7. The comparator 1 detects the phase difference between a reference signal fref and the output fosc of the divider 7 and drives the next-stage charge pump 3 as UP and DN signals. The charging/discharging current of the pump 3 is decided by the circuit 2. As voltage smoothed by the filter 4, the output of the pump 3 is inputted to the converter 5 to be converted to a current output and drives the oscillator 6. The stability of the device including resistance 17 and resistance 12 is secured by the circuit 2 and the converter 5.

73. 发明专利

JP2000339055A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000339055A
公开(公告)日：2000-12-08
申请号：JP14766499
申请日：1999-05-27
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAZAKI SUKEYUKI , TACHIZAWA TAKESHI , TAKADA KIWAMU , UCHIYAMA KUNIO , NISHII OSAMU , HASEGAWA KIYOSHI , AOKI HIROKAZU , KOKUBO MASARU
IPC分类号： G06F1/04 , G06F1/06 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03L7/07 , H03L7/081 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To stop a clock signal generation circuit simultaneously with turning the operation of an internal circuit to a stopped state, to quickly output a clock signal from the clock signal generation circuit when the circuit is restored to normal operation and to reduce power consumption when the circuit is in the stopped state. SOLUTION: A signal oscillated from a crystal oscillator or an external clock signal is inputted from a terminal xtal or extal and a mode terminal mod8 selects either one of the signal from the crystal oscillator and the external clock signal and inputs the selected signal to an oscillation circuit OSC. The frequency of the input clock signal is divided into a required value by a frequency division circuit DIV1. The frequency divided clock signal clk12 is inputted to a phase synchronizing loop circuit PLL1 and an output clock signal 1 from a circuit selected by a selector circuit SEL3 is distributed to the inside of an LSI through a frequency division circuit DIV2. The circuit PLL1 has clock signal stabilizing time more than 40 periods of a clock and the clock signal stabilizing time of a delay locked loop circuit DLL1 is 2 to 3 periods.

74. 发明专利

JP2000332586A POWER-ON RESET CIRCUIT 失效
公开(公告)号：JP2000332586A
公开(公告)日：2000-11-30
申请号：JP13994999
申请日：1999-05-20
申请人： HITACHI LTD
发明人： MIYAZAKI SUKEYUKI , MIZUNO HIROYUKI , TACHIBANA MASARU , ONO TAKEKAZU , KOKUBO MASARU , AKAZAWA TAKASHI , NODA TAKAAKI
IPC分类号： G06F1/24 , G05F1/10 , H03K17/22
摘要： PROBLEM TO BE SOLVED: To provide a power-on reset circuit which can accurately generate a reset signal even in the case of a momentary break wherein source voltage is momentarily cut off and is recovered immediately. SOLUTION: The power-on reset circuit is composed of a switch circuit 10 and a charging circuit 11 which charges the power-on reset circuit with a delay behind the rise of source voltage, a 1st discharging circuit 12 which discharges electric charges accumulated in the circuit part when the source voltage drops, a waveform shaping circuit 13 which detects the voltage of the charging circuit being above a certain constant level and generates a reset signal or reset undoing signal, and a 2nd discharging circuit 14 which raises the ground level of the waveform shaping circuit by the threshold voltage of a MOS transistor. Consequently, when the source voltage drops or is cut off, the output signal level also transits with voltage decrease so momentary variation in source voltage can be dealt with adequately.

75. 发明专利

JP2000091941A FREQUENCY BAND SELECTING METHOD OF PORTABLE TELEPHONE 失效
公开(公告)号：JP2000091941A
公开(公告)日：2000-03-31
申请号：JP25968898
申请日：1998-09-14
申请人： HITACHI LTD
发明人： KOKUBO MASARU , TANAKA SATOSHI , TAKIGAWA KUMIKO , YAMAWAKI DAIZO
IPC分类号： H04B1/38 , H04B1/3822
摘要： PROBLEM TO BE SOLVED: To eliminate the need for increasing input/output pins when a PLL synthesizer is integrated on the same semiconductor by detecting the set value of the counter of the feedback loop of a phase-synchronizing circuit and frequency bands to be used while inputting the set value, and selecting frequency bands corresponding to the detected outputs. SOLUTION: A transmitting and receiving circuit 14 which uses a PLL- synthesizer incorporated transmitting and receiving LSI is a transmitting and receiving circuit constituted by using a PLL-synthesizer incorporated transmitting and receiving LSI which includes a PLL synthesizer 1 and has a receiving circuit 11 and a transmitting circuit 12 integrated partially on the same semiconductor. The PLL synthesizer 1 has a band detecting circuit 15 which detects a frequency band that the transmitting and receiving circuit 14 uses according to a data value set in a register 5. A signal BAND for selecting the frequency band of the transmitting and receiving circuit 4 is supplied from the band detecting circuit 15 in the PLL synthesizer 1. The receiving circuit 11 and transmitting circuit 12 select the frequency band with the signal BAND. There is no special band switching signal from a B.B.LSI 2.

76. 发明专利

JPH11298302A FREQUENCY VARIABLE OSCILLATION CIRCUIT, PHASE SYNCHRONOUS CIRCUIT USING THE SAME AND CLOCK SYNCHRONOUS CIRCUIT 失效
公开(公告)号：JPH11298302A
公开(公告)日：1999-10-29
申请号：JP10142398
申请日：1998-04-13
申请人： HITACHI LTD
发明人： KO CHIYOUKYU , KOKUBO MASARU
IPC分类号： H03K3/354 , H03K3/03 , H03L7/089 , H03L7/099 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To obtain a variable oscillation frequency of a wide range with low power supply voltage by constructing differential amplifier circuits and a positive feedback circuit formed by connecting its input and output terminals in a crossed manner with complementary amplifier circuits consisting of pMOS and nMOS transistors and controlling current of the circuit to be a variable delay circuit. SOLUTION: The pMOS transistors 30 to 33 and the nMOS transistors 34 to 37 form a complementary amplifier circuit, a pair of complementary amplifier circuits forms a differential amplifier circuit and two differential amplifier circuits form a positive feedback circuit. When differential signals Vin1 and Vin2 are inputted, the differential amplifier circuits alternately charge floating capacities Cs1 and Cs2. The nMOS transistor 38 receives a frequency control signal Vcont at its gate, controls a discharge current and masks a variable delay circuit operate. Some 0.7 V threshold voltage is given to only one transistor that is turned on about the complementary amplifier circuits and the nMOS transistor 38 has only to give some 0.3 V that is necessary to operate in a saturation area.

77. 发明专利

JPH1098376A PHASE LOCKED LOOP 失效
公开(公告)号：JPH1098376A
公开(公告)日：1998-04-14
申请号：JP24958496
申请日：1996-09-20
申请人： HITACHI LTD
发明人： HORI KAZUYUKI , KOKUBO MASARU , YAMAWAKI DAIZO
IPC分类号： H03L7/093 , H03L7/08 , H03L7/087 , H03L7/089
摘要： PROBLEM TO BE SOLVED: To provide a phase locked loop which is the mode change-over type of a high-speed mode and low-noise mode. SOLUTION: Plural number of charge pumps CP1 and CP2 are connected to a loop filter, so as to hold at least one resistance r2 between a current output terminal and capacitance c1. Nand and nor in the outputs PU and PD of a phase frequency comparator 1 are obtained, a nor signal is adopted as the clock of D-FF64 and a signal obtained by delaying a nand signal by a delay element 63 for the portion of a short time dt is adopted as data of D-FF64, so that lock detection is executed. Based on this, the conductivity of the charge pump CP2 is controlled. The both of the loop band and a zero point of an open loop transmission function are changed only by changing the current value of the charge pump CP2.

78. 发明专利

JPH08265149A PHASE COMPARATOR AND FREQUENCY SYNTHESIZER USING THE PHASE COMPARATOR 失效
公开(公告)号：JPH08265149A
公开(公告)日：1996-10-11
申请号：JP6458195
申请日：1995-03-23
申请人： HITACHI LTD
发明人： HORI KAZUYUKI , KOKUBO MASARU
IPC分类号： H03L7/183 , H03L7/085
摘要： PURPOSE: To attain a high speed sampling by providing a clock phase difference generating means, an integration device, a differential sawtooth wave circuit and a filter circuit so as to provide an output of a phase difference between a reference frequency and an input signal. CONSTITUTION: A clock phase difference generating circuit 10 generates M kinds of clock signals CK0 -CKM-1 whose phase differs by 1/(Mfr) each from a reference clock signal CK with a frequency fv. Suppose that outputs of differential sawtooth wave circuits 200 -20M-1 are obtained synchronously with a timing of the signal CK, a sample value becomes definite for every virtual clock signal whose frequency is Mfd being a multiple of M of the signal CK. Then M-sets of adders 500 -0 50M-1 and a delay device 60 make high speed integration at a sampling frequency Mfr. Then the resulting signal is outputted by (M+1) sets of multipliers 700 -70M, M-sets of adders 800 -80M-1 and a multiplier 90 via the M-stages of moving mean filter circuits operated at a high speed by the sampling frequency Mfr.

79. 发明专利

JPH07212234A D/A CONVERTER AND FREQUENCY SYNTHESIZER USING THIS D/A CONVERTER 失效
公开(公告)号：JPH07212234A
公开(公告)日：1995-08-11
申请号：JP613094
申请日：1994-01-25
申请人： HITACHI LTD
发明人： HORI KAZUYUKI , KOKUBO MASARU
IPC分类号： H03L7/18 , H03L7/093 , H03M1/66 , H03M1/68 , H03M1/74 , H03M3/02
摘要： PURPOSE:To improve the accuracy of an output signal from the D/A converter using interpolation based on delta/sigma modulation and to suppress the fluctuation of an output frequency from the frequency synthesizer using the D/A converter. CONSTITUTION:This D/A converter is provided with a delta/sigma modulator 100 for performing the delta/sigma modulation to the low-order (n) bits of an N-bit input digital signal, first and second signal outputting devices 10 and 11 for outputting first and second signals to be used for selecting respective current source switch cells 402 corresponding to high-order (N-n) bits and high- order (N-n) bits + 1LSB, signal selector circuit 12 for selecting any one of first and second signals based on the output change of the delta/sigma modulator 100, and filter circuit 500 for smoothing the total sum of output currents from the respective current source switch cells 402 turned to an output state corresponding to the first or second signal selected by the signal selector circuit 12.

80. 发明专利

JPH06334518A LOCK DETECTING CIRCUIT FOR FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH06334518A
公开(公告)日：1994-12-02
申请号：JP11811293
申请日：1993-05-20
申请人： HITACHI LTD
发明人： ITO TAKAYASU , TAZAKI YUICHI , KOKUBO MASARU
IPC分类号： H03L7/095 , H03L7/18
摘要： PURPOSE:To detect the locking of the frequency synthesizer by comparing difference values of phase difference information by phase comparison periods with a specific value. CONSTITUTION:In a stable state at the time of transition of an oscillation frequency, the low-order N bits of numeric data are a varying part and in a transition state, the bits above the low-order N bits vary. For the purpose, it is only decided whether the varying part of the numeric data is the low-order N bits or not. Namely, a difference circuit 23 calculates differences of phase comparison data (numeric data) by the phase comparison periods of a differential phase comparator 18. The stable state is decided when the data of the output signal of this difference circuit 23 do not exceed the low-order N bits and the transition state is decided when the low-order N bits are exceeded. Then the output signal of this difference circuit 23 is compared by the comparator 24 with the specific value to decide whether the frequency synthesizer is in the transition state or stable state.

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