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1. 发明专利

JP2000339055A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000339055A
公开(公告)日：2000-12-08
申请号：JP14766499
申请日：1999-05-27
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAZAKI SUKEYUKI , TACHIZAWA TAKESHI , TAKADA KIWAMU , UCHIYAMA KUNIO , NISHII OSAMU , HASEGAWA KIYOSHI , AOKI HIROKAZU , KOKUBO MASARU
IPC分类号： G06F1/04 , G06F1/06 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03L7/07 , H03L7/081 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To stop a clock signal generation circuit simultaneously with turning the operation of an internal circuit to a stopped state, to quickly output a clock signal from the clock signal generation circuit when the circuit is restored to normal operation and to reduce power consumption when the circuit is in the stopped state. SOLUTION: A signal oscillated from a crystal oscillator or an external clock signal is inputted from a terminal xtal or extal and a mode terminal mod8 selects either one of the signal from the crystal oscillator and the external clock signal and inputs the selected signal to an oscillation circuit OSC. The frequency of the input clock signal is divided into a required value by a frequency division circuit DIV1. The frequency divided clock signal clk12 is inputted to a phase synchronizing loop circuit PLL1 and an output clock signal 1 from a circuit selected by a selector circuit SEL3 is distributed to the inside of an LSI through a frequency division circuit DIV2. The circuit PLL1 has clock signal stabilizing time more than 40 periods of a clock and the clock signal stabilizing time of a delay locked loop circuit DLL1 is 2 to 3 periods.

2. 发明专利

JP2000298532A TIMING CONTROL CIRCUIT DEVICE 失效
公开(公告)号：JP2000298532A
公开(公告)日：2000-10-24
申请号：JP10754299
申请日：1999-04-15
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAZAKI SUKEYUKI , HASEGAWA KIYOSHI , KOKUBO MASARU , AOKI HIROKAZU , ISHIBASHI KOICHIRO
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H03K5/13
摘要： PROBLEM TO BE SOLVED: To quickly execute phase synchronization, to adjust a phase difference without depending on an output load based on clock signal distribution or the like and to attain low skew and low power consumption in a timing control circuit for synchronizing a phase difference between an input clock signal and an output clock signal. SOLUTION: The timing control circuit device is constituted of a rough timing control circuit CDLL11 for roughly adjusting a phase difference between an input clock signal and an output clock signal, a fine timing control circuit FDLL11 for finely adjusting the phase difference and a rough/fine conversion circuit CONV11 for transmitting a clock signal from the circuit CDLL11 to the circuit FDLL11. The circuit FDLL11 highly accurately adjusts the phase difference between an input clock signal clkin11 and an output clock signal clkout11 by using a roughly adjusted signal to remove the phase difference.

3. 发明专利

JPH06231583A STORAGE WITH CHANGEABLE ACCESS SYSTEM 失效
公开(公告)号：JPH06231583A
公开(公告)日：1994-08-19
申请号：JP1726293
申请日：1993-02-04
申请人： HITACHI LTD
发明人： PARASHIOSU ARUBERUTO , UCHIYAMA KUNIO , AOKI HIROKAZU , HANAWA MAKOTO
IPC分类号： G06F3/08 , G11C11/401 , G11C11/407 , G11C11/413
摘要： PURPOSE:To obtain a storage which can dynamically cope with a number of application. CONSTITUTION:An access system to a storage 100 is set externally through a transmission control circuit using a signal for controlling the access system and is controlled so that it can cope with the access system of a decoder and an I/O interface and data are input to or output from a memory array corresponding to the input of an address using subsequent signals for controlling access, thus accessing to data with a transmission system which matches a plurality of applications and data control systems and enlarging the application range of a system using the title device.

4. 发明专利

JPH05120013A DATA PROCESSOR HAVING BRANCH INSTRUCTION BUFFER 失效
公开(公告)号：JPH05120013A
公开(公告)日：1993-05-18
申请号：JP28103091
申请日：1991-10-28
申请人： HITACHI LTD
发明人： NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F9/38 , G06F9/42
摘要： PURPOSE:To speed up the branch processing of a microprocessor and to especially speed up a non-conditional branch instruction including a return instruction. CONSTITUTION:A branch instruction address, a branch destination address, and a branch instruction type are made into a group and they are held in a branch instruction buffer BW102 as branch history information. A return buffer RB103 holding a return address is provided. Retrieval is executed by using a prefetch address. At the time of hit, the branch destination address of either BW102 or RB103 is selected by using the branch instruction type, and the prefetch address is switched so as to execute prebranching. An overhead at the time of branching can be made zero. A data processor can be applied to all the branch instructions including the return instruction.

5. 发明专利

JPH0395795A MULTIPORT MEMORY 失效
公开(公告)号：JPH0395795A
公开(公告)日：1991-04-22
申请号：JP23113089
申请日：1989-09-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HATANO SUSUMU , OOISHI TSURATOKI , KITANO JUN , NISHIMOTO KENJI , NAGASHIMA YASUSHI , KIKUCHI TAKASHI , SAIKOU YASUHIKO , FURUNOMA TOSHIHIKO , SASAKI KOTOKO , UCHIYAMA KUNIO , AOKI HIROKAZU , NISHII OSAMU
IPC分类号： G11C11/41
摘要： PURPOSE:To reduce energy consumption by controlling access operation from an input/output port in one part to a static form and controlling access operation from the remaining input/output port to a dynamic form. CONSTITUTION:A first control circuit 3 to control the access operation through an input/output port 4 in one part to the static form, which always select word lines WL1i and WL2i while following up the change of an input address signal, a second control circuit 7 to control the access operation through a remaining input/output port 8 to the dynamic form which synchronizes the operation to a clock are provided. In a data input/output system to be dynamically interfaced, a current does not flow from a bit line loading element through the selection register of a memory cell 10 and further the driving register of the memory cell 10 normally in a chip selecting state. Thus, the energy consumption can be reduced.

6. 发明专利

JPH0210450A PREFETCH CONTROL SYSTEM FOR CACHE MEMORY 失效
公开(公告)号：JPH0210450A
公开(公告)日：1990-01-16
申请号：JP15912188
申请日：1988-06-29
申请人： HITACHI LTD
发明人： NISHII OSAMU , UCHIYAMA KUNIO , AOKI HIROKAZU , NAGASHIMA YASUSHI
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To increase the processing speed of a processor by taking actions of access such as direct increase and repetition into consideration and executing prefetch at the time of profiting from application of prefetch. CONSTITUTION:A processor 10 which controls and executes operation is provided with an instruction decoding part 13 which reads out an instruction to decode the meaning of the instruction and an instruction executing part 19 which executes the instruction in accordance with the decoded results. A cache memory 11 includes an address array 16, a data array 17, and a control logic 19, and the access type of a control logic 19 is detected by a signal which is outputted form the processor 10 and indicates the classification of access, and a prefetch start circuit 24 is started in accordance with the detection result.

7. 发明专利

JPH0210446A BUFFER STORAGE DEVICE 失效
公开(公告)号：JPH0210446A
公开(公告)日：1990-01-16
申请号：JP16209588
申请日：1988-06-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIE YASUHIKO , FUKUDA HIROSHI , KIKUCHI TAKASHI , AOKI HIROKAZU , UCHIYAMA KUNIO , OOISHI KANJI , HATANO SUSUMU
IPC分类号： G06F12/08
摘要： PURPOSE:To shorten the waiting time of an MPU by providing a data buffer (block buffer), where one-block components of data can be stored at a time, between the internal data bus and the data memory part of a cache memory. CONSTITUTION:A block buffer 18 where one-block components of data can be stored at a time is provided between an internal data bus 17b and a data memory 12 of a cache memory 1, and data is transferred between the block buffer 18 and the data memory 12 with a unit larger than that for data transfer between the cache memory 1 and a main memory. Thus, one-block components of data to be transferred to the main memory or data transferred from the main memory are collectively stored in the bloc buffer 18, and the MPU can access the data memory 12 even during the block transfer between the cache memory 1 and the main memory to shorten the waiting time of the MPU.

8. 发明专利

JPH01320555A BUFFER STORAGE DEVICE 失效
公开(公告)号：JPH01320555A
公开(公告)日：1989-12-26
申请号：JP15569888
申请日：1988-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI TAKASHI , FUKUDA HIROSHI , SAIKOU YASUHIKO , OOISHI KANJI , HATANO SUSUMU , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/08
摘要： PURPOSE:To improve throughput by providing plural buffers for write to hold an address for write and data, and comprising a device of a register of dual port. CONSTITUTION:A directory memory 1 and a data memory compare an address inputted from a CPU with a tag address stored in the memory 1. Simultaneously, since they perform the comparison of the addresses in a store buffer, it is possible to read/write the data by the CPU with the minimum machine cycles without making access to a main memory even when noncoincidence is obtained in a comparison result with the memory 1 if coincidence is obtained in the comparison result of the addresses. In addition to that, since registers (6a-6d) of dual port format are provided in the buffer 6, it is possible to execute the write on the data memory 2 or the main memory even when the write cycle of the memory by the CPU continues, thereby, the throughput can be improved.

9. 发明专利

JPH01234951A BUFFER STORAGE SYSTEM AND BUFFER STORAGE CONTROL DEVICE 失效
公开(公告)号：JPH01234951A
公开(公告)日：1989-09-20
申请号：JP6265688
申请日：1988-03-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUKUDA HIROSHI , SAIE YASUHIKO , KIKUCHI TAKASHI , OOISHI TSURATOKI , HATANO SUSUMU , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/10 , G06F12/08 , G06F12/12
摘要： PURPOSE:To prevent data necessary for a system or the like from being lacked from a cache memory by making an address area including specific data correspond to a way not to be controlled at its replacement by a least recently used (LRU) control circuit or the like. CONSTITUTION:In a set associative type cache memory, ways FB not to be controlled at the replacement by the LRU control circuit 1 are respectively formed in a directory memory 2 and a data memory 3 independently of ways A-D to be controlled at their replacement by the circuit 1 and an address setting means for setting up address areas to be allocated to the ways is formed to switch the ways in accordance with an address applied to access. The address area including specific data is made to correspond to the ways FB not to be controlled at their replacement by the circuit 1 or the like. Consequently, data necessary for the system can be prevented from being lacked from the cache memory.

10. 发明专利

JPS63124150A ADDRESS CONVERTING SYSTEM 失效
公开(公告)号：JPS63124150A
公开(公告)日：1988-05-27
申请号：JP26963386
申请日：1986-11-14
申请人： HITACHI LTD
发明人： TAKAGI KATSUAKI , AOKI HIROKAZU , NAKAGAWA NORIO
IPC分类号： G06F12/10
摘要： PURPOSE:To ensure the fine control for sharing a virtual address space with no conflict by providing a type field containing plural flags, an address field and a protection field. CONSTITUTION:A type field (Type) consists of a flag RA showing whether the restorage is needed or not, a flag US which designates a space in a restorage mode, and a flag PM which designates use or non-use of the protection information on a restoring destination. While an address field (Addr) includes a logical or physical address in response to the flag RA. Then a protection field (Prot) includes the protection information on read R, write W and execution E. Then it is decided based on the Type whether the restoration is carried out or not after a descriptor is read. If so, the Addr is defined as a logical address to perform conversion of address again. If not, the Addr is defined as a physical address and put into the access of a main memory. Thus a virtual address space can be finely shared and furthermore controlled with no conflict.

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