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61. 发明专利

JP2004173089A Semiconductor integrated circuit for communication and radio communication system 有权
公开(公告)号：JP2004173089A
公开(公告)日：2004-06-17
申请号：JP2002338250
申请日：2002-11-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HAYASHI NORIO , SHINPO JIRO
IPC分类号： H03B1/00 , H03B5/32 , H03B5/36 , H03L7/23 , H04B1/40
CPC分类号： H04B1/406 , H03B5/366 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for communication with a built-in oscillation circuit, which allows a user to choose an external component for the reference oscillation circuit freely between a piezoelectric transducer or an oscillation module without increasing the number of external components or terminals.
SOLUTION: In the semiconductor integrated circuit, two external terminals (P1, P2) are arranged to correspond to the oscillation circuit. One external terminal (P1) is connected to the control terminal (base terminal) of a transistor (Q1) composing the oscillation circuit to make a passage for feeding part of the output of the transistor (Q1) back to the control terminal (P1), thereby making a composition for oscillation. The other external terminal (P2) is connected to a power source voltage terminal via a resistance element (R2) having a high resistance value. Capacitance elements (C1, C2) are connected between the external terminals (P1, P2). When a piezoelectric transducer is connected to the external terminal (P1), the external terminal (P2) is kept at a constant electric potential. When an electronic component for oscillation (oscillation module) is connected to the terminal (P1), the terminal (P2) is kept open.
COPYRIGHT: (C)2004,JPO

63. 发明专利

JP2003510943A Phase locked loop frequency generation circuit and the receiver to use the circuit 审中-公开
公开(公告)号：JP2003510943A
公开(公告)日：2003-03-18
申请号：JP2001527444
申请日：2000-09-15
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィ
发明人：アールマーシャル，ポール
IPC分类号： H03L7/22 , H03L7/08 , H03L7/187 , H03L7/23 , H04B1/26
CPC分类号： H03L7/0802 , H03L7/23
摘要： (57)【要約】周波数発生回路は、低電流消費で低速整定時間の第１の精密なＰＬＬ周波数シンセサイザ回路と（ＦＳ２）と、高電流消費で高速整定時間の第２の粗いＰＬＬ周波数シンセサイザ回路と（ＦＳ１）と、最終出力周波数を供給するための第１と第２の周波数シンセサイザ回路の出力を加算的に結合する信号結合回路（３６）を有する。実質的に同時にロックするように、第２の周波数シンセサイザ回路に電圧を与えるのに先だって、第１の周波数シンセサイザ回路に十分に電圧を与えるられる。全体的な電流消費は、単一のＰＬＬ周波数シンセサイザが最終周波数を発生するのに使用される場合よりも低い。

64. 发明专利

JP3380812B2 Pll frequency synthesizer and portable terminal using the pll frequency synthesizer 失效
公开(公告)号：JP3380812B2
公开(公告)日：2003-02-24
申请号：JP54370198
申请日：1997-04-14
申请人：三菱電機株式会社
发明人：和広森
IPC分类号： H03L3/00 , H03L7/093 , H03L7/099 , H03L7/183 , H03L7/23 , H03L7/18 , H03L7/087 , H04Q7/32
CPC分类号： H03L7/099 , H03L3/00 , H03L7/093 , H03L7/183 , H03L7/23

65. 发明专利

JP2002517118A 失效
公开(公告)号：JP2002517118A
公开(公告)日：2002-06-11
申请号：JP2000551483
申请日：1999-05-21
IPC分类号： H03D7/16 , H03L7/099 , H03L7/14 , H03L7/18 , H03L7/23 , H04B1/26 , H04B1/403 , H04B1/40

66. 发明专利

JP3268138B2 失效
公开(公告)号：JP3268138B2
公开(公告)日：2002-03-25
申请号：JP23537994
申请日：1994-09-29
IPC分类号： H03B28/00 , H03D7/16 , H03J7/06 , H03L7/107 , H03L7/16 , H03L7/18 , H03L7/183 , H03L7/185 , H03L7/23 , H04B1/26 , H04B1/30 , H04B1/3822 , H04B1/40

67. 发明专利

JP2002076889A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JP2002076889A
公开(公告)日：2002-03-15
申请号：JP2000268409
申请日：2000-08-31
申请人： ALPS ELECTRIC CO LTD
发明人： AOKI KAZUHARU , ASANO SHOICHI
IPC分类号： H03L7/22 , H03B21/02 , H03L7/08 , H03L7/197 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To provide a frequency synthesizer that reduces a lockup time. SOLUTION: The frequency synthesizer is provided with a 1st voltage controlled oscillator 11 that is controlled by a 1st PLL circuit 13 and outputs a 1st oscillation signal, a 2nd voltage controlled oscillator 21 that is controlled by a 2nd PLL circuit 23 and outputs a 2nd oscillation signal, and a mixer 30 that outputs a signal being a sum or a difference between the 1st and 2nd oscillation signals. The 1st voltage controlled oscillator 11 is oscillated at an interval of a 1st step frequency, the 2nd voltage controlled oscillator 21 is oscillated at an interval of a 2nd step frequency lower than the 1st step frequency, and a reference frequency of the 1st PLL circuit 13 is selected higher than a reference frequency of the 2nd PLL circuit 23.

68. 发明专利

JP2001136065A DUAL LOOP PHASE LOCKED LOOP DEVICE 失效
公开(公告)号：JP2001136065A
公开(公告)日：2001-05-18
申请号：JP2000282715
申请日：2000-09-18
申请人： SONY UK LTD
发明人： HARPHAM SIMON
IPC分类号： H03L7/22 , H03L7/08 , H03L7/087 , H03L7/185 , H03L7/193 , H03L7/197 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To provide a dual loop phase locked loop device(PLL) with low power consumption that is suitably integrated into a silicon monolithic integrated circuit. SOLUTION: The dual loop phase locked loop device employs two PLLs. An output signal from the 1st PLL is fed back to a mixer provided after a 1st stage frequency divider in a feedback loop of the 2nd PLL. Since the mixer by frequency division by the 1st stage frequency divider is operated at a low frequency, the power consumption of the device can be reduced. The 2nd PLL is phase-locked with an output of a comparison signal from the mixer. The output signal from the 1st PLL is fed back to the mixer via an intermediate frequency divider. The mixer adopts a digital system and consists of a D flip- flop.

69. 发明专利

JP2001502157A 失效
公开(公告)号：JP2001502157A
公开(公告)日：2001-02-13
申请号：JP51189699
申请日：1998-07-16
IPC分类号： H03L7/22 , H03L7/06 , H03L7/193 , H03L7/197 , H03L7/23 , H04B1/26

70. 发明专利

JP2000151284A DIRECT DIGITAL SYNTHESIZER 失效
公开(公告)号：JP2000151284A
公开(公告)日：2000-05-30
申请号：JP30791799
申请日：1999-10-29
申请人： LUCENT TECHNOLOGIES INC
发明人： JOHNSON ROBERT EVEREST
IPC分类号： G06F1/02 , G06F1/03 , H03B28/00 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To operate a direct digital synthesizer at a very high frequency and to generate a highly accurate frequency by providing a D/A converter that suitably converts a digital waveform value outputted form a programmable read only memory into an analog wave value to the direct digital synthesizer. SOLUTION: The digital synthesizer 18 is provided with a counter 10 that is incremented by a prescribed fixed increment 'C' (where C is an integer) in response to reception of a clock input, with the programmable read only memory (L.U.T) 12 that provides an output of a digital wave value in response to the reception of an output from the counter 10 and also with the D/A converter (D.A.C.) 14 that converts the digital wave value outputted from the programmable read only memory 12 into an analog wave value, Thus, the digital synthesizer can be operated at a very high frequency by using the counter with the increment designated especially in this way and can produce a frequency with high precision.

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