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61. 发明专利

JP2001185726A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001185726A
公开(公告)日：2001-07-06
申请号：JP2000349183
申请日：2000-11-16
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To realize a fine MOS transistor wherein a thin gate oxide film is arranged, metal is used as gate material, a source/drain region is formed by self alignment, a channel region is shallow and a gate length is at most 0.5 μm. SOLUTION: This MOS transistor consists of a source region, a channel region, a drain region, an interlayer oxide film formed on a region between the source region and the drain region, a gate oxide film which is formed on the channel region by self alignment, and a gate electrode which is formed on the channel region via the gate oxide film by self alignment.

62. 发明专利

JPH11243089A SIMULATION METHOD OF STRESS 失效
公开(公告)号：JPH11243089A
公开(公告)日：1999-09-07
申请号：JP4342198
申请日：1998-02-25
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO , NAKAKUBO TSUKASA
IPC分类号： H01L21/316 , H01L21/00
摘要： PROBLEM TO BE SOLVED: To obtain an accurate simulation result by giving the effect of stiffness change when silicon is changed to oxide as an initial stress increment for calculating stress, and by repeating stress calculation until an entire structure including silicon is balanced with force. SOLUTION: An oxidation seed diffusion calculation in an oxide is made based on a diffusion coefficient, a reaction coefficient, and a viscosity coefficient corresponding to a stress distribution at a starting point, and an oxidation flux vector (q) at the interface between silicon 1 and oxide 2 is obtained. Then, the silicon/oxide interface is moved in the direction of oxidation flux by a distance vector dx. Then, a thermal distortion increment, a creep distortion increment, and the like incidental to each material are given to an entire device structure for calculating stress, a displacement increment and a stress are obtained, and a shape is updated according to a displacement increment dv being obtained. Then, while the stress is being updated, force balance is checked, and a calculation is repeated until balancing is reached.

63. 发明专利

JPH1167892A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1167892A
公开(公告)日：1999-03-09
申请号：JP21457097
申请日：1997-08-08
申请人： TOSHIBA CORP
发明人： SAITO TOMOHIRO , USHIKU YUKIHIRO
IPC分类号： H01L21/76 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent the deterioration of an element characteristic, by forming an element separation insulating film which covers the side wall of an element separation groove and protrudes from the surface of an element forming area on the element separation insulating film which is buried to the middle of the element separation groove. SOLUTION: A buried oxidized film 5 is formed on the whole face and it is etched until the upper side wall of a trench groove is exposed. The upper corner of the element forming area is exposed. A polycrystalline silicon film 6 is formed on the whole face. Then, a silicon nitride film 3 and the unnecessary polycrystalline silicon film 6 on the buried oxide film 5 are removed, so that the polycrystalline silicon film 6 on the boundary of the element forming area and the trench groove does not come under the element forming area. The polycrystalline silicon film 6 is oxidized by a thermal oxidizing method and it is changed to the silicon oxide film 6a. Thus, the upper corner part of the element forming area is covered by the silicon oxide film 6a, and it can prevent the upper side wall of the trench groove from being exposed when removing the buffer oxide film 2.

64. 发明专利

JPH1093093A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1093093A
公开(公告)日：1998-04-10
申请号：JP24628996
申请日：1996-09-18
申请人： TOSHIBA CORP
发明人： YAGISHITA JUNJI , USHIKU YUKIHIRO
IPC分类号： H01L29/786 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To enable solving problems of gate material which remains behind and the deterioration of an element characteristic by forming a pair of source/ drain regions being opposed through a gate electrode respectively, on the surface of each side surface of a semiconductor layer. SOLUTION: It becomes possible to prevent effectively a semiconductor layer 12 from being etched, if a protective insulating film 13 is provided on the whole top surface of the semiconductor layer 12, for example, even if long- time etching with an extent of not leaving a gate material behind to be a possible cause for an interwiring short-circuit in the lower part of the semiconductor layer 12 is performed, in an etching process at the forming of a gate electrode 4. Accordingly, the removal of the gate material in the lower part of the semiconductor layer is made possible, without etching the semiconductor layer 12 in the source/drain region. Further, on this occasion exposure of the upper part corner sections of the semiconductor layer is reduced, so it becomes possible to prevent the deterioration of the gate withstand voltage and the element characteristics, such as a sub-threshold characteristic.

65. 发明专利

JPH09264801A METHOD FOR MEASURING STRESS/STRAIN 失效
公开(公告)号：JPH09264801A
公开(公告)日：1997-10-07
申请号：JP7754996
申请日：1996-03-29
申请人： TOSHIBA CORP
发明人： YAGISHITA JUNJI , SAITO TOMOHIRO , USHIKU YUKIHIRO
IPC分类号： G01L1/24 , G01N21/65 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To accurately obtain the stress/strain near the inside surface of an sample by obtaining, based on measurement, at least one of the stress and strain near the exposed inside surface of a solid sample. SOLUTION: Firstly, an inside surface 2 of a solid sample 1 is exposed. Then, with the use of a laser Raman spectrum analysis, a Raman shift amount or a Raman scatter intensity, or bath of them near the exposed inside surface are measured, and based on thus obtained Raman shift amount or Raman scatter intensity or bath of them, a stress distribution 3 near the exposed inside surface are obtained. Then, based on the measuring result, an elasticity analysis is performed with 3-demention stress simulation, so that a stress distribution 3a on the inside surface, before the inside surface 2 is exposed (before destruction), is obtained by calculation. Thus, the stress distribution in the depth direction of the sample 1 is accurately obtained.

66. 发明专利

JPH098047A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH098047A
公开(公告)日：1997-01-10
申请号：JP15944895
申请日：1995-06-26
申请人： TOSHIBA CORP
发明人： TAKAHASHI MINORU , INABA SATOSHI , OKAYAMA YASUNORI , USHIKU YUKIHIRO , YAGISHITA JUNJI
IPC分类号： H01L21/76 , H01L21/322 , H01L21/8238 , H01L27/092
摘要： PURPOSE: To restrain generation of crystal defects and metallic impurities due to defects inside an element region and increase a junction leak current or improve lowering of dielectric strength of a gate oxide film in a CMOS-type integrated circuit with a buried isolation structure. CONSTITUTION: For example, a groove 11a is selectively formed on the surface of a p-type Si board 11 and a buried isolation region 12 is formed by burying an oxide film in an inside thereof. A plurality of pMOS elements 13 and nMOS elements 15 are formed alternately in the isolation region 12. A gettering region 17 is formed in an outer circumferential part of an element region 14 wherein the pMOS element 13 is formed and an element region 16 wherein the nMOS element 15 is formed.

67. 发明专利

JPH08139325A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08139325A
公开(公告)日：1996-05-31
申请号：JP23250695
申请日：1995-09-11
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO , MIZUNO TOMOHISA , YOSHIMI MAKOTO , TERAUCHI MAMORU , KAWANAKA SHIGERU
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/49
摘要： PURPOSE: To provide a semiconductor device capable of improving element characteristics and also of restricting short channel effect by punch-through phenomena. CONSTITUTION: A substrate 1 having a semiconductor element region with a projected shape, a gate electrode formed via a gate insulation film on the upper surface and side surface of element region, a first conductive type source region and drain region provided so as to form a channel region on the top surface of the element region by sandwiching the gate electrode are arranged, and a high-concentration impurity region 13 containing a second conductive type impurities having a concentration higher than that of the channel region which is formed inside a portion having a projected shape and below the channel region.

68. 发明专利

JPH08139177A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08139177A
公开(公告)日：1996-05-31
申请号：JP23307195
申请日：1995-09-11
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO , INABA SATOSHI , TAKAHASHI MINORU , YAGISHITA JUNJI , OKAYAMA YASUNORI , MATSUSHITA YOSHIAKI , KUBOTA HIROYASU , TSUCHIYA NORIHIKO , NUMANO MASAKUNI , HAYASHI YOSHIKI
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108
摘要： PURPOSE: To prevent the isolation of an embedded element and the crystalline defect due to the implantation of impurities by forming a groove on a semiconductor substrate with the element on a surface region and embedding a substance having different thermal expansion coefficient from that of the substrate at least in the part of the groove. CONSTITUTION: An embedding material 3 having different thermal expansion coefficient from that of a semiconductor substrate 1 is embedded in the first groove 2 of the substrate 1, and a stress is generated in the groove 2. A semiconductor layer 4 to become an element forming region is formed on the substrate 1, and two element forming regions are electrically isolated by a second groove 5 and an embedding material 6. The material 3 in the groove 2 may have either tensile or compressive stress. When a crystalline defect is generated in the deep part of the substrate 1 in advance by he large stress, the stress is alleviated later, and a distortion is reduced. Thus, the defect by the stress is almost eliminated in the layer 4 formed newly at the upper part, and a junction leakage current can be reduced.

69. 发明专利

JPH05251384A 失效
公开(公告)号：JPH05251384A
公开(公告)日：1993-09-28
申请号：JP15822992
申请日：1992-06-17
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO , IIJIMA TADASHI , NISHIYAMA AKIRA
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L21/90
摘要： PURPOSE:To provide a semiconductor which is capable of preventing a drop in the reliability of this semiconductor device caused by disconnection in a connection hole and an increase in contact resistance. CONSTITUTION:This semiconductor device is formed on a semiconductor substrate 11 where the device comprises an insulation film 14 having a contact hole 15 on an impurity diffusion layer 13 formed on this semiconductor substrate 11, a reaction preventative film 16 formed on the sides and the bottom of the contact hole 15 and an Ni3Si film 17 which fills in the contact hole 15.

70. 发明专利

JPH0284731A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0284731A
公开(公告)日：1990-03-26
申请号：JP23686688
申请日：1988-09-21
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/768
摘要： PURPOSE:To bury and form a conductor layer in a plurality of contact holes of different depth while keeping excellent flatness by exposing the conductor layer in shallow contact holes, covering the conductor layer with photo resist in deep contact holes, and etching the whole surface in the above-mentioned state. CONSTITUTION:On a semiconductor substrate 1 on which elements are formed, an insulating film 7 is deposited; a plurality of contact holes 81, 82 of different depth are formed by selectively etching the insulating film 7; then by selective vapor growth method, conductor layers 92, 91 are buried and formed, so as to protrude in the shallow contact hole 82 and fill as far as midway in the deep contact hole 81; next, the whole part is coated with photo resist 10; by developing, the conductor layer 92 is exposed in the shallow contact hole 8, and the conductor layer 91 is covered with the photo resist in the deep contact hole 81: by etching, the protruding part of the conductor layer 92 in the shallow contact hole S2 is eliminated, and, at the same time, a part of the insulating film 7 is eliminated. After that, for example, the photo resist 10 is eliminated and Al wiring is formed, thereby completing a MOS integrated circuit.

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