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1. 发明专利

JP2014203844A ＭＥＭＳ装置及びその製造方法审中-公开
标题翻译： MEMS器件及其制造方法
公开(公告)号：JP2014203844A
公开(公告)日：2014-10-27
申请号：JP2013076091
申请日：2013-04-01
申请人：株式会社東芝 , Toshiba Corp
发明人： SAITO TOMOHIRO
IPC分类号： H01G5/16 , B81B3/00 , B81B5/00 , B81C1/00 , H01H49/00 , H01H59/00
CPC分类号： B81B3/0086 , B81B2201/0221 , H01G5/18
摘要：【課題】可変容量キャパシタやスイッチ等で優れた特性を有する。【解決手段】MEMS装置であって、支持基板10上に設けられた第1の電極21と、第1の電極21上に、少なくとも一つの端部が第1の電極21と重なるように該第1の電極21に対向配置され、且つ第1の電極21との対向方向に可動可能に設けられた第2の電極22と、支持基板10上に設けられ、第2の電極22を弾性的に支持する梁部23と、を具備している。そして、第2の電極22の端部と対向する領域の第1の電極21の上面の高さを、第2の電極22の中央部と対向する領域の第1の電極21の上面の高さよりも低くしている。【選択図】図2
摘要翻译：要解决的问题：提供一种在可变电容电容器，开关等中具有优异特性的MEMS器件。解决方案：MEMS器件包括：设置在支撑基板10上的第一电极21; 设置成与第一电极21相对的第二电极22，使得其至少一个端部与第一电极21重叠，在第一电极21的上方，并且设置成能够在面向第一电极21的方向上移动; 以及设置在支撑基板10上并弹性地支撑第二电极22的梁部23。在与第二电极22的端部相对的区域中，第一电极21的上表面的高度低于在与第二电极22的中心部分相对的区域中的第一电极21的顶表面。

2. 发明专利

JP2014180732A Mems device and manufacturing method thereof 有权
标题翻译： MEMS器件及其制造方法
公开(公告)号：JP2014180732A
公开(公告)日：2014-09-29
申请号：JP2013057278
申请日：2013-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： B81B7/02 , B81C1/00 , H01G5/16 , H01H49/00 , H01H59/00
CPC分类号： B81B3/0086 , B81B2201/0221
摘要： PROBLEM TO BE SOLVED: To provide a MEMS device capable of suppressing bending of an upper electrode caused by the edge of a bottom electrode, and having a capacity characteristic excellent in a variable capacity capacitor or a switch.SOLUTION: A MEMS device includes: a first electrode 21 provided on a support substrate 10; an embedded insulator film 34 embedded into a peripheral part of the first electrode 21; a second electrode 22 arranged oppositely to the first electrode 21, having an end part provided so as to jut out furthermore to the outside than the end part of the first electrode 21, and provided movably to the opposite direction to the first electrode 21; and a beam part 23 provided on support substrate 10, for supporting elastically the second electrode 22.
摘要翻译：要解决的问题：提供一种能够抑制由底部电极的边缘引起的上部电极的弯曲并且具有优异的可变容量电容器或开关的容量特性的MEMS器件。解决方案：MEMS器件包括：设置在支撑基板10上的第一电极21; 嵌入在第一电极21的周边部分中的嵌入式绝缘膜34; 与第一电极21相对配置的第二电极22，具有设置成比第一电极21的端部向外侧突出的端部，并且与第一电极21相反的方向可移动地设置; 以及设置在支撑基板10上的用于弹性地支撑第二电极22的梁部23。

3. 发明专利

JP2012191052A Mems and manufacturing method thereof 有权
标题翻译： MEMS及其制造方法
公开(公告)号：JP2012191052A
公开(公告)日：2012-10-04
申请号：JP2011054334
申请日：2011-03-11
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： H01G5/16 , B81B3/00 , B81C1/00
CPC分类号： H01G5/18 , B81B2201/018 , B81B2201/0221 , B81B2203/0109 , B81C1/00611 , B81C2201/0126
摘要： PROBLEM TO BE SOLVED: To provide a MEMS capable of obtaining excellent element characteristics.SOLUTION: A MEMS manufacturing method comprises: a step of forming a lower electrode 12A on a substrate 10; a step of forming an auxiliary structure 13A which is brought into an electrically floating state so as to be adjacent to the lower electrode 12A, on the substrate 10; a step of forming a sacrificial film on the lower electrode 12A, the auxiliary structure 13A, and the substrate 10; a step of forming an upper electrode 16 on the sacrificial film; and a step of removing the sacrificial film and disposing the upper electrode 16 above the lower electrode 12A via a cavity 21A. The sacrificial films formed on the lower electrode 12A and the auxiliary structure 13A have a flat upper surface. The upper electrode 16 formed on the sacrificial film has a flat lower surface.
摘要翻译：要解决的问题：提供能够获得优异的元件特性的MEMS。解决方案：MEMS制造方法包括：在基板10上形成下电极12A的步骤; 在基板10上形成与下部电极12A相邻的电浮动状态的辅助结构13A的工序; 在下电极12A，辅助结构13A和基板10上形成牺牲膜的步骤; 在牺牲膜上形成上电极16的步骤; 以及去除牺牲膜并经由空腔21A将上电极16设置在下电极12A上方的步骤。形成在下电极12A和辅助结构13A上的牺牲膜具有平坦的上表面。形成在牺牲膜上的上电极16具有平坦的下表面。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012024861A Mems apparatus 审中-公开
标题翻译： MEMS装置
公开(公告)号：JP2012024861A
公开(公告)日：2012-02-09
申请号：JP2010162913
申请日：2010-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： B81B3/00 , H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06
CPC分类号： H01L21/764 , H01G5/18
摘要： PROBLEM TO BE SOLVED: To provide a MEMS apparatus in which a parasitic capacitance between a substrate and a MEMS device and warpage of the substrate are controlled.SOLUTION: The MEMS apparatus includes: a recess opened to a surface; the substrate having an insulator, an air gap, or an insulator and an air gap formed in the recess; an insulating layer formed on the substrate; and the MEMS device having a signal line formed on the insulating layer; wherein the position of the signal line in a direction parallel to the surface of the substrate overlaps the position of the recess in the direction.
摘要翻译：要解决的问题：提供一种其中控制衬底和MEMS器件之间的寄生电容以及衬底翘曲的MEMS装置。解决方案：MEMS装置包括：向表面开口的凹部; 所述基板具有形成在所述凹部中的绝缘体，气隙或绝缘体和气隙; 形成在所述基板上的绝缘层; 并且所述MEMS器件具有形成在所述绝缘层上的信号线; 其中，所述信号线在与所述基板的表面平行的方向上的位置与所述凹部的所述方向的位置重叠。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2006339512A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006339512A
公开(公告)日：2006-12-14
申请号：JP2005164179
申请日：2005-06-03
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO MOTOYUKI , SEKINE KATSUYUKI , SAITO TOMOHIRO , NAKAJIMA KAZUAKI , EGUCHI KAZUHIRO , YAGISHITA JUNJI
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823462 , H01L21/82345 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To include an element having a gate insulating film composed of high dielectric substances of different materials and allow to prevent a deterioration of characteristic of an element.
SOLUTION: The semiconductor device includes a semiconductor substrate 2 having a first and second element areas separated by an element separating area 4, a first gate insulating film 6b composed of a high dielectric substance located in the first element area, a first gate electrode 8b located in the first gate insulating film, first source/drain areas 20, 24 located in the first element area of both sides of the first electrode, a second gate insulating film 14b composed of a high dielectric substance of a material different from the first insulating film located in the second element area, a second gate electrode 16b located on the second gate insulating film, and second source/drain areas 20, 24 located in the second element area of both sides of the second gate electrode.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：包括具有由不同材料的高电介质物质构成的栅绝缘膜的元件，并且可以防止元件的特性劣化。解决方案：半导体器件包括具有由元件分离区域4隔开的第一和第二元件区域的半导体衬底2，由位于第一元件区域中的高介电物质构成的第一栅极绝缘膜6b，第一栅极位于第一栅极绝缘膜中的电极8b，位于第一电极两侧的第一元件区域中的第一源极/漏极区域20,24，由不同于第一栅极绝缘膜的材料的高介电性材料构成的第二栅极绝缘膜14b 位于第二元件区域中的第一绝缘膜，位于第二栅极绝缘膜上的第二栅极电极16b和位于第二栅电极两侧的第二元件区域中的第二源极/漏极区域20,24。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005116633A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005116633A
公开(公告)日：2005-04-28
申请号：JP2003345956
申请日：2003-10-03
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L29/66545 , H01L29/66795 , H01L29/66803 , H01L29/78621
摘要： PROBLEM TO BE SOLVED: To provide fin type field effect semiconductor device and a method of manufacturing the same in which the source/drain region of the LDD structure may be formed easily without formation of a side wall insulating film.
SOLUTION: In this manufacturing method, after a gate electrode (or dummy gate) is formed to a fin type silicon layer, a first impurity region is formed by introducing an impurity into the fin type silicon layer using the gate electrode (or dummy gate) as a mask. Next, the gate electrode (or dummy gate) is etched for reduction in size thereof. Thereafter, a second impurity region is formed by introducing an impurity to the fin type silicon layer using the gate electrode (or dummy gate) of the reduced size as the mask.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供翅片型场效应半导体器件及其制造方法，其中可以容易地形成LDD结构的源极/漏极区域而不形成侧壁绝缘膜。解决方案：在这种制造方法中，在对鳍型硅层形成栅电极（或伪栅极）之后，通过使用栅极电极（或者）将杂质引入鳍型硅层来形成第一杂质区域虚拟门）作为掩模。接下来，蚀刻栅电极（或伪栅极）以减小其尺寸。此后，通过使用减小尺寸的栅极（或虚拟栅极）作为掩模将杂质引入鳍型硅层来形成第二杂质区。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005093856A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005093856A
公开(公告)日：2005-04-07
申请号：JP2003327517
申请日：2003-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a gate insulating film is formed on a semiconductor substrate only by one time of a film formation process and gate electrodes having conductive materials of different job functions are then formed.
SOLUTION: The method of manufacturing the semiconductor device includes steps of: forming the gate insulating film on the semiconductor substrate having a first device region and a second device region, forming a masking all over the surface and then selectively etching the masking to form an opening for exposing a portion of the gate insulating film positioned in the first device region; forming a first conductive material film all over the masking including the opening, patterning it to form the patterned first conductive material film at least in the portion of the gate insulating film positioned in the first device region and then removing the exposed masking by etching; forming a second conductive material film having a job function different from that of the first conductive material film on the gate insulating film including the patterned first conductive material film; and forming a first gate electrode including the first conductive material film on the gate insulating film in the first device region, and forming a second gate electrode composed of the second conductive material film on the gate insulating film in the second device region.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种半导体器件的制造方法，在半导体衬底上仅通过成膜工艺一次形成栅极绝缘膜，并且然后具有不同工作功能的导电材料的栅极电极形成。解决方案：制造半导体器件的方法包括以下步骤：在具有第一器件区域和第二器件区域的半导体衬底上形成栅极绝缘膜，在整个表面上形成掩模，然后选择性地蚀刻掩模形成用于暴露位于第一装置区域中的栅极绝缘膜的一部分的开口; 在包括所述开口的所述掩模之上形成第一导电材料膜，至少在位于所述第一器件区域中的所述栅极绝缘膜的部分中图案化以形成所述图案化的第一导电材料膜，然后通过蚀刻去除所述暴露的掩模; 在包括图案化的第一导电材料膜的栅极绝缘膜上形成具有与第一导电材料膜不同的作用功能的第二导电材料膜; 以及在所述第一器件区域中的所述栅极绝缘膜上形成包括所述第一导电材料膜的第一栅电极，以及在所述第二器件区域中的所述栅极绝缘膜上形成由所述第二导电材料膜构成的第二栅电极。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005005510A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005005510A
公开(公告)日：2005-01-06
申请号：JP2003167803
申请日：2003-06-12
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TOMOHIRO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/41733 , H01L29/458 , H01L29/6656 , H01L29/78621
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for suppressing lowering of a current driving force and to provide a method of manufacturing the device.
SOLUTION: A contact area can be increased by forming a silicide layer 9 divided into stripes in order to reduce an interface resistance between a source/ drain resistance, particularly between the silicide layer 9 and impurity diffusing region 8. Particularly, a current driving force of a MOS transistor of the SOI substrate is improved. Regarding the SOI substrate, a single crystal silicon semiconductor layer is formed on the silicon substrate via an insulating layer such as silicon oxide film. This semiconductor layer is formed of a silicon active layer and an element isolating region for defining silicon active layer. This transistor comprises a polycrystal silicon gate electrode 5 covered with a side wall insulating film 6, a source/drain region, and a silicide layer 9 and a gate insulating film 4 formed on this source/drain region.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于抑制电流驱动力降低的半导体器件，并提供一种制造器件的方法。解决方案：通过形成划分成条纹的硅化物层9可以增加接触面积，以便减少源/漏电阻之间的界面电阻，特别是在硅化物层9和杂质扩散区8之间。特别地，电流提高了SOI衬底的MOS晶体管的驱动力。关于SOI衬底，通过诸如氧化硅膜的绝缘层在硅衬底上形成单晶硅半导体层。该半导体层由硅有源层和用于限定硅有源层的元件隔离区形成。该晶体管包括被覆在该源/漏区上的侧壁绝缘膜6，源极/漏极区以及硅化物层9和栅极绝缘膜4的多晶硅栅电极5。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2000049348A SEMICONDUCTOR DEVICE WITH ELEVATED SOURCE DRAIN STRUCTURE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000049348A
公开(公告)日：2000-02-18
申请号：JP14975099
申请日：1999-05-28
申请人： TOSHIBA CORP
发明人： MIYANO KIYOTAKA , MIZUSHIMA ICHIRO , TSUNASHIMA YOSHITAKA , SAITO TOMOHIRO
IPC分类号： H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress the generation of a short-channel effect and a junction leakage current by forming a gap between the bottom surface of a gate-side insulation film and a silicon substrate by etching a liner and a gate oxide film in a crosswise direction. SOLUTION: For example, an SiO2 liner 10 and a gate sidewall SiN film 11 are used, and further the SiO2 liner 10 on the bottom surface of the gate sidewall SiN film 11 is etched in a crosswise direction by a specific amount, thus forming a gap with specific dimensions between the bottom surface of the gate sidewall SiN film 11 and the silicon substrate 1. After that, by allowing silicon to be subjected to epitaxial growth, a facetless epitaxial silicon film 12 can be formed at a part in contact with the gate sidewall SiN film 11. Therefore, by injecting an impurity ion onto a substrate surface via the facetless epitaxial silicon film 12 and forming a source diffused layer 14 and a drain diffused layer 15, the generation of a short-channel effect and a junction leakage current can be suppressed.

10. 发明专利

JPH11238858A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11238858A
公开(公告)日：1999-08-31
申请号：JP3876798
申请日：1998-02-20
申请人： TOSHIBA CORP
发明人： SAITO TOMOHIRO , SUGURO KYOICHI
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To suppress oxygen deficiency in a sintering treatment and to prevent an augmentation in a leakage current in a capacitor and the deterioration of the dielectric strength of the capacitor, by a method wherein a dielectric material for the capacitor is not reduced but is heat-treated in an atmosphere containing at least an oxidizing agent. SOLUTION: An element isolation film 12 and a MOS transistor 13 are formed in a silicon substrate 11 and thereafter, an interlayer insulating film 14 is deposited on the substrate 11 and an open part to reach source and drain diffused layers of the transistor 13 is formed in the film 14. Subsequently, a contact 15 is formed in this open part and a capacitor 16, which is connected with the contact 15, formed. After the capacitor 16 is formed, a sintering treatment is performed. The condition of the sintering treatment is, for example, made on a condition that a temperature is set at 400 deg.C and forming gas of 10% of a hydrogen partial pressure and 10% of water vapor partial pressure is used. As a result, an Ru material which is used for a capacitor electrode is not oxidized, and a dielectric material which is used for a capacitor insulating film is not reduced. Accordingly, the separation of an oxygen element from the capacitor, such as oxygen deficiency, is prevented and a leakage current in the capacitor and the like are lessened.

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