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61. 发明专利

JPH06337890A CALLING AND GUIDE SYSTEM 失效
公开(公告)号：JPH06337890A
公开(公告)日：1994-12-06
申请号：JP12870493
申请日：1993-05-31
申请人： HITACHI LTD
发明人： INOUE KIYOSHI , OKI MASARU , OHIRA EIJI , SAGAWA HIROHIKO , SAGARA KAZUHIKO , SAKIYAMA ASAKO , OBUCHI YASUNARI , TODA YUJI
IPC分类号： H04Q7/14 , G06Q10/08 , G06Q50/22 , G06Q50/28 , H04B7/26 , G06F15/21 , G06F15/24
摘要： PURPOSE:To provide a chance for smoothly receiving service such as medical examination and treatment to hearing handicapped persons and to provide a call and guide system for executing emergency guide. CONSTITUTION:An identification(ID) number inputted by an input means 101 on a reception desk is written in its corresponding pacient data base 130 and informed to a consultation room in which the pacient is to be examined and a calling means 160 is requested to call the pacient by operation in the room. The means 160 oscillates an oscillator in a radio receiver carried by the pacient and transmits a message to a display unit. Thereby an efficient calling and guide method can be provided to a hearing handicapped pacient who can not easily receive a sound signal.

62. 发明专利

JPH06337630A PORTABLE TYPE SIGN LANGUAGE INPUT DEVICE 失效
公开(公告)号：JPH06337630A
公开(公告)日：1994-12-06
申请号：JP12570393
申请日：1993-05-27
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , OHIRA EIJI , OBUCHI YASUNARI , INOUE KIYOSHI , SAGAWA HIROHIKO , SAKIYAMA ASAKO , OKI MASARU , TODA YUJI
IPC分类号： G06F3/033 , G09B21/00
摘要： PURPOSE:To obtain a device which improves portability and easily useability and can be applied in a public place by separating an oscillator held by an auditory sense handicapped person and a portable computer held by a sound listener, and exchanging their information by a radio wave. CONSTITUTION:This device consists of input devices 1, 2 and a terminal 3 which an auditory sense handicapped person A possesses, and a portable computer 4 which a sound listener B possesses. In the input devices 1, 2, a position of a wrist or a finger is converted to an electric signal, and a signal is sent to the terminal 3 by a radio wave. In the terminal 3, these signals are further summarized and sent to the portable computer 4 by a radio wave. In the portable computer 4, these results are analyzed and a sentence is displayed. As for a function of the input devices 1, 2, an electro myograph input type and a space coordinate input type exist. For instance, in the case of the electro myograph input type, the input device 2 and the terminal 3 are used, a position of each finger is measured by an electro myograph of a wrist by using the input device 2, and to the terminal 3, a signal corresponding to a position of each finger, and a space coordinate and acceleration of the input device 2 in which the terminal 3 is an origin are inputted.

63. 发明专利

JPH06337627A SIGN LANGUAGE INTERPRETING DEVICE 失效
公开(公告)号：JPH06337627A
公开(公告)日：1994-12-06
申请号：JP12570593
申请日：1993-05-27
申请人： HITACHI LTD
发明人： SAGAWA HIROHIKO , OKI MASARU , OHIRA EIJI , SAGARA KAZUHIKO , OBUCHI YASUNARI , SAKIYAMA ASAKO , INOUE KIYOSHI , TODA YUJI
IPC分类号： G09B21/00 , G06F17/28 , G06T1/00 , H04N7/18 , G06F15/38 , G06F15/62
摘要： PURPOSE:To constitute the device so that an input person can confirm and correct easily a result of translation of inputted sign language or voice language by combining and displaying displays executed by plural means such as a sentence of voice language, a word name, illustration of sign language of words, sign language CG, and an image of sign language executed by an auditory sense handicapped person by the setting desired by a user. CONSTITUTION:A sign language word recognizing part 3 outputs a recognized sign language word train d4, and it is inputted to a sign language voice language converting part 5. In the sign language voice language converting part 5, a semantic relation between the words is analyzed by utilizing a word dictionary 6 with respect to the sign language word train d4, and a sentence d6 of voice language is generated and outputted by making up for a particle and an inflection. To a sound listener side display part 7, a sign language image d1 inputted from a video camera 1, a sign language word train candidate d4 recognized by the sign language word recognizing part 3, a sentence candidate d6 of voice language generated by the sign language voice language converting part 5, and a sign language CG image candidate d11 generated by a sign language CG generating part 14 are inputted, and in accordance with setting of a user, their combination is determined and displayed.

64. 发明专利

JPH0682674B2 失效
公开(公告)号：JPH0682674B2
公开(公告)日：1994-10-19
申请号：JP22573684
申请日：1984-10-29
申请人： HITACHI LTD
发明人： NAKAMURA TOORU , NAKAZATO KAZUO , PPONMA NORYUKI , SAGARA KAZUHIKO , KUBO SEIJI , HAYASHIDA TETSUYA , MATSUMOTO MASAAKI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/417 , H01L29/732

65. 发明专利

JPH02172231A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02172231A
公开(公告)日：1990-07-03
申请号：JP32579488
申请日：1988-12-26
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/8222 , H01L27/06 , H01L29/732
摘要： PURPOSE:To facilitate high integration by a method wherein a buried layer belonging to an active region is divided into a plurality of regions electrically separated from each other by a plurality of insulating walls which are vertical to a substrate and pierce through the buried layer and reach the substrate. CONSTITUTION:A buried layer 2 is divided into a plurality of regions by insulating walls 9 provided vertically to a substrate 1. As the respective regions are electrically separated from each other, they can be used as independent emitter regions. With this constitution, if only one active region is formed on the buried layer 2, a multi-emitter structure in which the buried layer 2 is utilized as a group of the independent emitter regions can be realized. Moreover, if this device is employed, a conventional LSI which requires a plurality of active regions can be realized with one active region, so that the highly integrated LSI can be realized.

66. 发明专利

JPH0267732A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0267732A
公开(公告)日：1990-03-07
申请号：JP21831288
申请日：1988-09-02
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , KOBAYASHI NOBUYOSHI , ONOUCHI YUKIHIRO , SAGARA KAZUHIKO , HONMA YOSHIO , NAKAMURA TORU
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/43 , H01L29/732
摘要： PURPOSE:To use a metal silicide film, having stable shape and characteristic, as a base lead-out electrode by causing the material composition of the base lead-out electrode to be a three layer film consisting of a polycrystalline silicon film/a metal silicide film/a polycrystalline silicon film. CONSTITUTION:When the material composition of a base lead-out electrode is such that said electrode is a three layer film consisting of a polycrystalline silicon film 10/a metal silicide film 11/a polycrystalline silicon film 12, even if thermal oxidation if effected, the polycrystalline silicon film 12, the uppermost layer, is oxidized to form an oxide film 15 for isolating both of an emitter and the base lead-out electrodes and the metal silicide film 11 is not oxidized, so that the problem as to consumption of the polycrystalline silicon film 10 and generation of stress at the interface can be eliminated. Further, because the lowermost polycrystalline silicon film 10 exists, the impurity diffusion for a tie-base into a monocrystalline silicon region 3 can be carried out from the polycrystalline silicon film 10 as usual, so that the controllability of electrical characteristics is maintained in good state. Moreover, the problem due to direct contact between the metal silicide film 11 and the monocrystalline silicon region 3 can also be eliminated. As the metal silicide film 11, silicide of a high melting point metal such as tungsten, titanium, etc., or silicide of a low melting point metal such as platinum is used.

67. 发明专利

JPH01135064A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01135064A
公开(公告)日：1989-05-26
申请号：JP29201887
申请日：1987-11-20
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , YADORI SHOJI , KOBAYASHI NOBUYOSHI , OJI YUZURU , MUKAI KIICHIRO , ITOU HIROYUKI , TAMAOKI YOICHI , HONMA NORIYUKI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/72 , H01L29/732
摘要： PURPOSE:To perform 1 or less of aspect ratio by employing a wiring material having excellent electromigration resistance and specific resistance of the same degree as that of aluminum. CONSTITUTION:An opening is formed at the part of the surface of an element, covered 300nm thick by a sputtering method with tungsten, and first layer tungsten wirings 9 having 500nm of minimum working size are formed by normal photographic technique and dry etching technique. A chemical vapor method using WF6 may be employed as a coating method of the tungsten in stead of the sputtering method. The resistivity of the obtained wirings 9 is 8-10muOMEGA.cm, which is approx. 2.5-3 times as large as that containing aluminum, 0.5% of Cu and 1% of Si. Thus, at least the tungsten or molybdenum is employed as the wirings, thereby performing an integrated circuit having 1 or less of aspect ratio even if a distance between the wirings is, for example, 0.5mum or less.

68. 发明专利

JPS6415974A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6415974A
公开(公告)日：1989-01-19
申请号：JP17114687
申请日：1987-07-10
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , KURE TOKUO , MURAKAMI HIDEKAZU , NAKAMURA TORU
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
摘要： PURPOSE:To unnecessitate a subcollector (colletor) region, and enable the miniaturization of an element, by applying a dielectric layer in an element isolation trench to a wiring layer as well as a filling layer for the trench, and using the inside of the element isolation trench as a region for leading out a collector (emitter) electrode. CONSTITUTION:By applying an ordinary lithography and a dry etching art, an element isolation trench 100 deeper than the diffusion depth of an n-type buried layer 2 is arranged around the N-type buried layer. An insulating film 7 is formed in the inside of the element isolation trench 100. An aperture part 70 is made in a part of the insulating film 7 on the side being in contact with the n-type buried layer 2. In the inside of the element isolation trench 100, dielectric material is flatly buried via the insulating film 7 to form a dielectric layer 12, and the surface of the element isolation trench 100 is covered an insulating film 8'. An aperture part 101 is made in a part of the insulating film 8', and a single crystal n-type epitaxial layer 3 is exposed. Successively, by using solid growth method and the like, single crystal silicon is formed on the aperture part 101 in which the epitaxial layer 3 is exposed, and a p-type diffusion layer 4 turning to polycrystal silicon is formed on the other region.

69. 发明专利

JPS62154785A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS62154785A
公开(公告)日：1987-07-09
申请号：JP29289885
申请日：1985-12-27
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI , IKEDA SEIJI , NAKAMURA TORU
IPC分类号： H01L29/78 , H01L21/225 , H01L21/265
摘要： PURPOSE:To miniaturize an MOS transistor and to enhance drain withstanding voltage, by providing a conducting layer, which is formed on a substrate through an insulating film so that the layer is contacted with the side parts of impurity doped regions that are formed in the surface region of a semiconductor layer protruded on the substrate, with a specified interval being provided. CONSTITUTION:A semiconductor layer 12 is protruded on a specified region of a substrate 11. Impurity doped regions 24 and 25, which have the reverse conductivity type with respect to the semiconductor layer 12, are formed in the surface region of the layer 12 with a specified interval being provided. A gate electrode 27 is formed at a part between the impurity doped regions 24 and 25 on the semiconductor layer 12 through an insulating film 13. A conducting layer 20 is formed on the substrate 11 through an insulating film 16 so that the layer 20 is contacted with the side parts of the impurity doped regions 24 and 25. For example, on an N-type epitaxial Si layer 12 on the P-type Si substrate 11, the P-type low impurity concentration source and drain regions 21 and 22 are formed. The N-type polycrystalline Si gate electrode 27 is provided through the gate SiO2 film 12. The P-type polycrystalline Si layer 20 and Al electrodes 28 and 29 are provided through the SiO2 film 16.

70. 发明专利

JPS6295870A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6295870A
公开(公告)日：1987-05-02
申请号：JP23514585
申请日：1985-10-23
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI , IKEDA SEIJI , NAKAMURA TORU
IPC分类号： H01L29/78 , H01L21/331 , H01L21/76 , H01L29/72 , H01L29/73
摘要： PURPOSE:To reduce junction capacity and improve propagation delay time by determining depth of element isolation groove formed through the n-type buried layer to a value larger than depth of the interface between the n-type buried layer and p-type substrate from the substrate surface. CONSTITUTION:An element isolation groove is provided through the n-type buried layer 2, the depth of this groove is set larger than the interface of the n-type buried layer 2 from the substrate surface and p-type Si substrate 1, junction capacitance (CTs) is reduced by making small the junction area, propagation delay time (tpa) is set fast and thereby high packing density and high operation rate of high performance bipolar transistor can be realized. As the other embodiment, the electrode 31 is used as the anode of SBD, while the electrode 13 as the cathode thereof. Thereby, the alpha ray resistance can be improved because of the p-type diffusion layer 7. Moreover, when the electrode 13 is used as the anode of SBD and the electrode 14 as the cathode thereof, the transient characteristic of diode can be improved because of small parasitic capacitance.

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