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61. 发明专利

JPS63285635A PROCESSOR CONTROL SYSTEM 失效
公开(公告)号：JPS63285635A
公开(公告)日：1988-11-22
申请号：JP12090887
申请日：1987-05-18
申请人： FANUC LTD
发明人： KINOSHITA JIRO
IPC分类号： G06F9/32 , G06F9/38 , G06F13/16 , G06F13/36
摘要： PURPOSE:To improve the processing capacity of a microprocessor by adding an exclusive instruction fetching bus to the microprocessor in addition to the normal address and data buses and connection an instruction storing memory to said instruction reading bus. CONSTITUTION:An exclusive instruction fetching bus 4 is added to a microprocessor 1 in addition to a normal address bus 2 and a normal data bus 3. Then an instruction storing memory 5 is connected to the bus 4. In other words, the microprocessor 1 fetches continuously the instructions via the bus 4 and carries out these instructions. Then the microprocessor 1 uses both buses 2 and 3 in a fetching cycle to read the next instruction and carries out this instruction. Thus it is possible to prevent the deterioration of the processing capacity of the microprocessor 1 due to an access of a low-speed memory, etc.

62. 发明专利

JPS63158657A COPROCESSOR CONTROL SYSTEM 失效
公开(公告)号：JPS63158657A
公开(公告)日：1988-07-01
申请号：JP30728686
申请日：1986-12-23
申请人： FANUC LTD
发明人： KURAKAKE MITSUO , KINOSHITA JIRO
IPC分类号： G06F15/16 , G06F9/38 , G06F12/00 , G06F15/167
摘要： PURPOSE:To reduce a burden in delivering data between a host processor and a coprocessor providing a shared RAM for delivering the data between a program memory exclusively used for the coprocessor and the host processor. CONSTITUTION:The program memory 6 which can be directly made access by the coprocessor 4 and the shared RAM5 which can be made access both by the host processor 1 and the processor 4. Accordingly, since the processor 4 has the exclusively used memory 6, the processor 1 writes plural arithmetic processings to be processed and the data required therefor in the RAM5, when it is informed to the processor 4, the processor 4 reads it to execute a required arithmetic processing. The result is written in the RAM5, when it is informed to the processor 1, the processor can read it and the burden of the processor 1 is reduced without transferring a command and the data for every individual operation.

63. 发明专利

JPS62243058A CONTROL METHOD OF INTERRUPTION FOR MULTI-PROCESSOR SYSTEM 失效
公开(公告)号：JPS62243058A
公开(公告)日：1987-10-23
申请号：JP8692186
申请日：1986-04-15
申请人： FANUC LTD
发明人： YONEKURA MIKIO , KINOSHITA JIRO
IPC分类号： G06F15/16 , G06F13/24 , G06F15/17 , G06F15/177
摘要： PURPOSE:To optionally increase an interrupting signal by combining an address and a data bus, by constituting the titled system so that a processor can recognize an interruption from a bit of an address corresponding to an address space and a mask bit of a register. CONSTITUTION:In the whole address space, addresses Addr 1-3 are allocated for an interruption. When an interrupting signal IS2 is inputted to an interruption controlling circuit 12 from the outside, the circuit 12 takes sole possession of a bus, and writes a bit data corresponding to the signal IS2 and the Addr 2 in advance in an address bus 4. A processor board 20 reads the address bus, decodes it and compares the contents of this bit data and a mask bit register 24. Also, a fact that a DO bit of a data bus is '1'. In such a state, by recognizing the interrupting signal to the processor, a CPU 21 starts to execute an interruption program.

64. 发明专利

JPS62136694A COLOR GRAPHIC APPARATUS 失效
公开(公告)号：JPS62136694A
公开(公告)日：1987-06-19
申请号：JP27860685
申请日：1985-12-11
申请人： FANUC LTD
发明人： KURAKAKE MITSUO , KINOSHITA JIRO
IPC分类号： G09G5/06 , G09G1/02 , G09G1/28 , G09G5/36

65. 发明专利

JPS6045498B2 失效
公开(公告)号：JPS6045498B2
公开(公告)日：1985-10-09
申请号：JP2009079
申请日：1979-02-22
申请人： FANUC LTD
发明人： KURAKAKE MITSUO , YAMAUCHI TAKASHI , KINOSHITA JIRO
IPC分类号： G11C11/401 , G11C11/4076 , G11C29/00 , G11C29/12

66. 发明专利

JP2002374175A Pattern generating method for burst error and detection /correction apparatus for burst error and byte error 有权
标题翻译：用于BURST错误和字节错误的BURST错误和检测/校正装置的模式生成方法
公开(公告)号：JP2002374175A
公开(公告)日：2002-12-26
申请号：JP2001180455
申请日：2001-06-14
申请人： Fanuc Ltd , Eiji Fujiwara , ファナック株式会社 , 英二藤原
发明人： FUJIWARA EIJI , KINOSHITA JIRO
IPC分类号： G06F11/10 , G11B20/18 , H03M13/17 , H04L1/00
CPC分类号： H03M13/17
摘要： PROBLEM TO BE SOLVED: To detect burst errors and byte errors in reception information, and to correct them in parallel.
SOLUTION: A syndrome S is determined from reception information D and a parity inspection matrix for correcting a burst error, having a length up to b bits. the syndrome S is inputted into burst error pattern generating circuits 2-1 through 2-p which overlap by b-1 bits with each other, with each having information framework of 2b-bit length. If the burst error is contained completely in the framework of one of the circuits 2-1 through 2-p, this burst error pattern is outputted. An error pattern calculating circuit 3 takes logical OR with an overlapping part from the outputs of the circuits 2-1 through 2-p. Exclusive OR of the output of the circuit 3 and the information D is taken, to obtain a correction information DS. Thus, burst error in the information D can be detected and corrected.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：检测接收信息中的突发错误和字节错误，并并行纠正。解决方案：从接收信息D和用于校正长度高达b比特的突发错误的奇偶校验矩阵确定校验子S。校正子S被输入到以b-1比特重叠的突发错误模式生成电路2-1至2-p，每个具有2b位长的信息框架。如果突发错误完全包含在电路2-1至2-p之一的框架中，则输出该突发错误模式。错误模式计算电路3从电路2-1至2-p的输出端与重叠部分进行逻辑或运算。采用电路3的输出和信息D的异或以获得校正信息DS。因此，可以检测和校正信息D中的突发错误。

67. 发明专利

JP2000298510A CONTROL DEVICE 失效
公开(公告)号：JP2000298510A
公开(公告)日：2000-10-24
申请号：JP10816299
申请日：1999-04-15
申请人： FANUC LTD
发明人： KINOSHITA JIRO , SASAKI KAZUYUKI , KUBO YOSHIYUKI
IPC分类号： G05B19/18 , G05B19/414
摘要： PROBLEM TO BE SOLVED: To provide a control device enabling a user to operate it at hand while observing machine operation, and when a fault occurs in the control device, allowing a control part to be simply replaced. SOLUTION: Control parts such as a CPU 101, memories 102, 104, a display part such as an LCD 111 connected to the control part and manual data input parts such as a keyboard 107 and a touch panel 109 are packaged in a portable casing as a 1st control device part 100 and a motor driving power supply part packaged in a portable casing and constituted of an I/O interface part, an inverter, etc., connected to an actuator and a sensor arranged on a machine is arranged in another casing as a 2nd control device part and both the control device parts are mutually connected through a communication means. When the 1st control device part is carried, manual operation can be executed while monitoring machine operation. When a fault occurs in the 1st control device part 100, the whole control device can be immediately restored by replacing the 1st control device itself with a new one.

68. 发明专利

JPH11259114A NUMERICAL CONTROLLER 失效
公开(公告)号：JPH11259114A
公开(公告)日：1999-09-24
申请号：JP7642798
申请日：1998-03-11
申请人： FANUC LTD
发明人： KURAKAKE MITSUO , KINOSHITA JIRO , KUMAKURA TATSURO
IPC分类号： B23Q15/00 , G05B19/408 , G05B19/409 , G05B19/4093
摘要： PROBLEM TO BE SOLVED: To provide a numerical controller capable of optionally and easily combining the arrangement positions of a numerical control part, a display control part and a machine operation part by using software prepared by a user without requiring a storage device having mechanism parts such as a hard disk. SOLUTION: An operating system to be executed in a semiconductor memory and software for display control are stored in a ROM 2d built in a display control part 2. A machine operation part 3 constituted of a keyboard 3a and a machine operation board 3b is connected to the display control part 2 and allowed to communicate with a numerical control part 1 in real time. Software prepared by a user is inputted from a data I/O equipment 7 through a communication part 2e and stored in a non-volatile memory 2c to execute it. Even when the control part 1 is separated from the control part 2, a display device 2k and the operation part 3 can be arranged close to each other, improving operability.

69. 发明专利

JPH11143789A BUS TRACING DEVICE 失效
公开(公告)号：JPH11143789A
公开(公告)日：1999-05-28
申请号：JP31773097
申请日：1997-11-05
申请人： FANUC LTD
发明人： KINOSHITA JIRO , AOYAMA KAZUNARI , OKAMURA YUKIO
IPC分类号： G06F11/28 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To provide a bus tracing device for specifying an error the cause of, storing data for analyzing the cause of the error, and continuously storing data for the analysis of the error. SOLUTION: Storage of data for the identification of the cause of an error as well as for the analysis of any specific cause of the error is made possible., by limiting a bus cycle fetching condition, and the data obtained by the fetch of the bus cycle are transferred to an arbitrary memory and stored so that data for the analysis of an error can be continuously stored. By monitoring the data in a bus 3, this device operates bus tracing for the retrieval of the cause of the error in a processing using a processor. An error data fetching means 10 including plural data storing means 13 is connected with the bus 3 connected with a processor 1, and this error data fetching means 10 successively fetches only the data of the bus cycle fulfilling the set fetching condition in the data storing means 13.

70. 发明专利

JPH10307603A DATA TRANSMISSION DEVICE 失效
公开(公告)号：JPH10307603A
公开(公告)日：1998-11-17
申请号：JP13451097
申请日：1997-05-09
申请人： FANUC LTD
发明人： KINOSHITA JIRO , KUMAKURA TATSURO , HIROHAMA HIDEYUKI
IPC分类号： G05B9/03 , G05B19/18 , G05B19/414 , G08B29/16 , H04L1/22 , H04Q9/00
摘要： PROBLEM TO BE SOLVED: To secure the safety of duplex communication and to facilitate connection between a control unit and peripheral equipment. SOLUTION: A transmission part 300 stores data of receivers (a) and (b) of switches which are interlocked by DMA(direct memory access) control circuits 306a and 306b, etc., in register files 304a and 304b having the same address. A serial data control circuit 302 reads data out to selectors 303a and 303b by specifying addresses in order and sends the stored data alternately by switching at intervals of a specific number of bits. A reception part 400 which receives composed serial data performs switching by a switching circuit 401 at intervals of the specific number of bits and converts the data into a parallel signal by S/P converters 403a and 403b, latches the signal by latch circuits 407a1 and 407b1 to 407am and 407bm, and perform ON/OFF control over relays R11a and R11b to Rmna and Rmnb according to the latch contents. Power is not connected unless both the corresponding relays to which the contacts are connected in series turn on.

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