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1. 发明专利

JPH11161326A NUMERICAL CONTROLLER 失效
公开(公告)号：JPH11161326A
公开(公告)日：1999-06-18
申请号：JP33945797
申请日：1997-11-26
申请人： FANUC LTD
发明人： KINOSHITA JIRO , MURAOKA YUTAKA
IPC分类号： G05B23/02 , G05B19/042 , G05B19/18
摘要： PROBLEM TO BE SOLVED: To provide the numerical controller which can monitor a receiving circuit inputting machine information. SOLUTION: The machine information from a machine side is received by independent systems and the received external signals are compared to monitor the reception state of the receiving circuit. One configuration of the numerical controller consists of independent receiving means 4 and 5 which input the external signals and monitor means 2 and 3 which compares the external signals received at least the two receiving means and monitors the receiving means according to the comparison result.

2. 发明专利

JPH07295622A CONTROL SYSTEM 失效
公开(公告)号：JPH07295622A
公开(公告)日：1995-11-10
申请号：JP8633194
申请日：1994-04-25
申请人： FANUC LTD
发明人： KINOSHITA JIRO , KUBO YOSHIYUKI
IPC分类号： B25J9/22 , B25J13/06 , G05B19/18 , G05B19/408 , G05B19/414
摘要： PURPOSE:To install an interactive data processor at a distance from an FA controller and make the interactive data processor access the memory in the FA controller directly. CONSTITUTION:When a request to access the memory 3 in a CNC 30 is outputted in an MMC 20, the access request is outputted by a remote access control means 1 to the CNC 30. An internal data input/output means 2 in the CNC 30, once receiving the access request, performs direct memory access(DMA) to the memory 3 to access a requested address. Then when the access request is a write request, data are written in the memory. Further, when the access request is a read request, on the other hand, specified data are outputted to the MMC 20. The remote access control means 1 in the MMC 20 receives the inputted data and transfers the data to the device which has outputted the access request. Thus, the MMC 20 is enabled to access the memory 3 in the CNC 30 directly.

3. 发明专利

JPH06309018A DATA MANAGEMENT SYSTEM FOR CNC 失效
公开(公告)号：JPH06309018A
公开(公告)日：1994-11-04
申请号：JP9262493
申请日：1993-04-20
申请人： FANUC LTD
发明人： KINOSHITA JIRO , AOYAMA KAZUNARI
IPC分类号： G05B19/18 , G05B19/414
摘要： PURPOSE:To easily add data on a user side and also easily confirm their use state as to the data management system for CNC which controls data added by option. CONSTITUTION:The selection command means 3 in the CNC 10 commands the selection of data to be added by screen operation, etc., among data stored in an external memory 1 such as a memory card. Further, the selection command means 3 also selectively commands the selection of data which are used so far and become unnecessary. A read/write execution means 4 reads the selected data to be added out of a data storage area 1a of the external memory 1 and writes them in an internal memory 5 such as a flash ROM. Further, the data which become unnecessary are deleted from the internal ROM 5. A data state recording means 6 records the name of the data read out of the external memory or deleted from the internal memory 5 and the date, the frequency of use, etc., in a data state storage area 1b.

4. 发明专利

JPH05216527A GRAPHIC INTERFERENCE CHECK DEVICE 失效
公开(公告)号：JPH05216527A
公开(公告)日：1993-08-27
申请号：JP1781592
申请日：1992-02-03
申请人： FANUC LTD
发明人： KINOSHITA JIRO , HAMADA YOICHI
IPC分类号： G05B19/4069 , G06F17/50
摘要： PURPOSE:To only generate one picture information to reduce the time and the labor by comparing two picture data (color information) of adjacent circuits with each other and discriminating interference to output an interrupt signal to a host CPU at the time when data (color information) of two picture elements whose setting is omitted and which should be checked for interference are adjacent to each other. CONSTITUTION:Picture information in a frame buffer 3 is outputted as a parallel signal to a P/S converter 4. This converter 4 converts the parallel signal to a serial signal by the command from a graphic controller 2 and outputs it. A latch circuit 7 latches data of picture elements of picture information, which is stored in the frame buffer 3, from the P/S converter 4 with one picture element as the unit. A comparing circuit 8 compares two adjacent picture element information out of two or more picture element information to be checked for interference, which are set from the host CPU, with each other with respect to outputs of the P/S converter 4 and the latch circuit 7, thus detecting the interference. The comparing circuit 8 outputs the interrupt signal to the host CPU 1.

5. 发明专利

JPH04143846A INTERFACE CONVERTER CIRCUIT 失效
公开(公告)号：JPH04143846A
公开(公告)日：1992-05-18
申请号：JP26743990
申请日：1990-10-04
申请人： FANUC LTD
发明人： KINOSHITA JIRO , AOYAMA KAZUNARI
IPC分类号： G06F13/12 , G05B19/05 , G05B19/18 , G05B19/414 , G06F12/04 , G06F13/16 , G06F13/38
摘要： PURPOSE:To prevent the deterioration of the data processing speed by providing an array converting means which converts an address and its data arrays based on the conversion data stored in a storage means. CONSTITUTION:The address signals outputted from an MPU are sent to a storage means 8 and a conversion command means 19. The means 19 decides whether the address designated by the received address signal and a data array of the address signal should be converted or not. If so, a conversion command signal is outputted to a storage means 8. The means 8 sends the conversion data to a data array converter circuit 14. Thus the circuit 14 converts the address and its data array based on the conversion data received from the means 8. As a result, the deterioration of the data processing speed is prevented.

6. 发明专利

JPH04120638A CACHE MEMORY CONTROLLING SYSTEM 失效
公开(公告)号：JPH04120638A
公开(公告)日：1992-04-21
申请号：JP24063290
申请日：1990-09-11
申请人： FANUC LTD
发明人： KINOSHITA JIRO , AOYAMA KAZUNARI
IPC分类号： G06F12/08
摘要： PURPOSE:To improve the program processing speed with a small cache memory capacity by dividing the area of a main memory into divisions and executing the program by only transferring the division where transferring valid information to a cache memory exists. CONSTITUTION:A numerical controller executes a program by validating the transfer of each division of a main memory 3 to a cache memory 21. When the processing time of a division 31 becomes shorter as compared with the processing time before validating the transfer, the controller turns on the valid information to be transferred in the divisions 31. On the contrary, the controller tuns off the divisions which require longer processing time. The transferring valid information is stored in the area 22 of the cache memory 21. Since a program is executed by deciding the transferring valid information to all divisions of the main memory 3 in such way, the processing time of the program is reduced with a small cache memory capacity.

7. 发明专利

JPH025104A ARITHMETIC PROCESSING UNIT 失效
公开(公告)号：JPH025104A
公开(公告)日：1990-01-10
申请号：JP15570988
申请日：1988-06-23
申请人： FANUC LTD
发明人： KINOSHITA JIRO
IPC分类号： G05B19/05
摘要： PURPOSE:To furthermore speed up the execution of a program by providing the title arithmetic processing unit with a function instruction processor corresponding to respective instructions, a byte logical operation instruction processor and a bit logical operation instruction processor to execute the program in parallel. CONSTITUTION:The function instruction processor 13, the byte loginal operation instruction processor 14 and the bit logical operation instruction processor 15 execute sequence programs stored in a ladder instruction memory 11 in parallel. Since the numbers of function instruction, byte logical operation instructions ad bit logical operation instructions are different in each sequence program and the execution speed of each instruction is also different, one processor should wait the end of an execution instruction based upon another processor. These processing is executed by an arbitration circuit 12. Thus, the sequence program can be more rapidly executed.

8. 发明专利

JPH01217604A SYNCHRONIZING CONTROL SYSTEM 失效
公开(公告)号：JPH01217604A
公开(公告)日：1989-08-31
申请号：JP4396188
申请日：1988-02-26
申请人： FANUC LTD
发明人： KURAKAKE MITSUO , KINOSHITA JIRO
IPC分类号： G05B19/18 , G05B19/19 , G05B19/4062
摘要： PURPOSE:To check a step-out state even with a superposed operation by simulating the follow-up error value of the single shift value of the superpose operation axis to subtract said error value from the follow-up error value of a servomotor control circuit for said operation axis for acquisition of the follow-up error value of the synchronizing operation axis and comparing this follow-up error value with the actual follow-up error value of the synchronizing operation axis. CONSTITUTION:The shift value of the synchronizing operation axis Z1 is superposed on a servomotor control circuit 10 of the superposed operation axis Z2. In this respect, the follow-up error value of the single shift value of the Z2 is simulated and subtracted from the follow-up error value of the circuit 10 of the Z2. Thus the error value of the Z1 is obtained. This obtained error value must be coincident with the follow-up error value of the circuit 10 of the Z1 as long as both axes Z2 and Z1 are normally working. Thus both error values are compared with each other so as to confirm whether both axes Z1 and Z2 are normally working or not.

9. 发明专利

JPH01149107A NUMERICAL CONTROLLER 失效
公开(公告)号：JPH01149107A
公开(公告)日：1989-06-12
申请号：JP30899487
申请日：1987-12-07
申请人： FANUC LTD
发明人： KINOSHITA JIRO
IPC分类号： G05B19/18 , G05B19/05 , G05B19/414 , G06F9/06
摘要： PURPOSE:To facilitate change, level up, or the like by storing a user program of a programmable controller (PC) in a unit independent of a management program and making this unit attachable and detachable. CONSTITUTION:A numerical controller 10 having the PC consists of a processor 11 which controls the whole of this controller 10, a ROM 12 in which the management program of the PC is stored, a printed board 20, and connectors 13 and 22 which connect them. A ROM 21 in which the user program of the PC is stored is mounted on the printed board 20. Since the management program can be user program of the PC are stored in units independent of each other, they are changed and have levels raised independently of each other and they are handled independently of each other.

10. 发明专利

JPH01116731A ACCESS CONTROL SYSTEM 失效
公开(公告)号：JPH01116731A
公开(公告)日：1989-05-09
申请号：JP27487287
申请日：1987-10-30
申请人： FANUC LTD
发明人： KINOSHITA JIRO , KAWAMURA FUMIO
IPC分类号： G06F9/38 , G06F12/02
摘要： PURPOSE:To attain access to a device while executing a data processing and to shorten access time by providing a next address generator, storing an address command from a microprocessor and generating an address to be accessed next. CONSTITUTION:A next address generator to receive the address command from a microprocessor 1 and to generate successively the addresses of the device to be accessed next is provided. The cycle of the processor 1 fetches data from a device 3 and outputs the next address command to the next address generator 2. By this command, the next address generator 2 generates the necessary address and accesses the device. While the next address generator accesses the device, the processor 1 executes an instruction fetch and a data processing. Thus, the access time is absorbed into the instruction fetch and data processing time of the processor 1 and for this, the access time to the device is shortened.

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