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1. 发明专利

JP4824784B2 Method and apparatus for decoding multiword information 有权
公开(公告)号：JP4824784B2
公开(公告)日：2011-11-30
申请号：JP2009043538
申请日：2009-02-26
申请人：メディアテックインコーポレイテッドMediatek Inc.
发明人：ウーウェン−イー , シエジア−ホーン , リンリー−リエン
IPC分类号： G11B20/18
CPC分类号： G11B20/18 , G11B20/1809 , G11B2020/1288 , G11B2220/2541 , H03M13/17 , H03M13/27 , H03M13/29

2. 发明专利

JP4620541B2 Error detection code calculation circuit, error detection code calculation method and a recording apparatus 有权
公开(公告)号：JP4620541B2
公开(公告)日：2011-01-26
申请号：JP2005226705
申请日：2005-08-04
申请人：ルネサスエレクトロニクス株式会社
发明人：剛生有山
IPC分类号： G11B20/18 , G11B20/10 , G11B20/12
CPC分类号： G11B20/18 , G11B2020/1272 , H03M13/11 , H03M13/17 , H03M13/29 , H03M13/2903 , H03M13/2906

3. 发明专利

JP2002374175A Pattern generating method for burst error and detection /correction apparatus for burst error and byte error 有权
标题翻译：用于BURST错误和字节错误的BURST错误和检测/校正装置的模式生成方法
公开(公告)号：JP2002374175A
公开(公告)日：2002-12-26
申请号：JP2001180455
申请日：2001-06-14
申请人： Fanuc Ltd , Eiji Fujiwara , ファナック株式会社 , 英二藤原
发明人： FUJIWARA EIJI , KINOSHITA JIRO
IPC分类号： G06F11/10 , G11B20/18 , H03M13/17 , H04L1/00
CPC分类号： H03M13/17
摘要： PROBLEM TO BE SOLVED: To detect burst errors and byte errors in reception information, and to correct them in parallel.
SOLUTION: A syndrome S is determined from reception information D and a parity inspection matrix for correcting a burst error, having a length up to b bits. the syndrome S is inputted into burst error pattern generating circuits 2-1 through 2-p which overlap by b-1 bits with each other, with each having information framework of 2b-bit length. If the burst error is contained completely in the framework of one of the circuits 2-1 through 2-p, this burst error pattern is outputted. An error pattern calculating circuit 3 takes logical OR with an overlapping part from the outputs of the circuits 2-1 through 2-p. Exclusive OR of the output of the circuit 3 and the information D is taken, to obtain a correction information DS. Thus, burst error in the information D can be detected and corrected.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：检测接收信息中的突发错误和字节错误，并并行纠正。解决方案：从接收信息D和用于校正长度高达b比特的突发错误的奇偶校验矩阵确定校验子S。校正子S被输入到以b-1比特重叠的突发错误模式生成电路2-1至2-p，每个具有2b位长的信息框架。如果突发错误完全包含在电路2-1至2-p之一的框架中，则输出该突发错误模式。错误模式计算电路3从电路2-1至2-p的输出端与重叠部分进行逻辑或运算。采用电路3的输出和信息D的异或以获得校正信息DS。因此，可以检测和校正信息D中的突发错误。

4. 发明专利

JPS5975732A Decoder 失效
标题翻译：解码器
公开(公告)号：JPS5975732A
公开(公告)日：1984-04-28
申请号：JP18637582
申请日：1982-10-22
申请人： Mitsubishi Electric Corp
发明人： NAMEKAWA TOSHIHIKO , KASAHARA MASAO , TOKIWA KINICHIROU , INOUE TOORU , OKAMURA SHIGERU
IPC分类号： H03M13/29 , H03M13/15 , H03M13/17
CPC分类号： H03M13/15 , H03M13/17
摘要： PURPOSE:To correct a fine random error when the random error occurs and to improve reliability by providing a switch which discriminates which of a random and a burst error corrected part an error correction is made at and switches both modes. CONSTITUTION:When a BCH code for correcting the random error is used, an error is corrected by a random error correcting function part 16 which is a conventional type decoder. If a mode discriminating circuit part 18 detects the error or wrong correction, the output of the random error correcting function part 16 is cut off by a switch 19 and information outputted from a burst error correcting function part 17 is selected and outputted to an output terminal 17. In other cases, the output of the random error correcting function part 16 is selected. Namely, the output vector outputted from the random error correction part 16 is inputted to a memory register 31 to find a syndrome S5 according to an equation. Similarly, an element alpha of a Galois field is multiplied from the output of the random error correction part 16 to find S6 according to the equation. When a single or double error occurs, an error correction 16 is made and S5 and S6 are both 0; and the switch 19 transfers the output of the error correction part 16 to the output terminal 7 through an OR gate 41.
摘要翻译：目的：当发生随机误差时纠正精细的随机误差，并通过提供一个开关来提高可靠性，该开关鉴别随机和突发纠错部分中的哪一个进行纠错并切换两种模式。构成：当使用用于校正随机误差的BCH码时，通过作为常规类型解码器的随机纠错功能部分16纠正错误。如果模式识别电路部分18检测到错误或错误的校正，则由开关19切断随机纠错功能部分16的输出，并且从脉冲串纠错功能部件17输出的信息被选择并输出到输出端子在其他情况下，选择随机纠错功能部分16的输出。即，从随机误差校正部分16输出的输出矢量被输入到存储寄存器31，以根据等式找到综合征S5。类似地，伽罗瓦域的元素α6从随机误差校正部分16的输出相乘，以根据等式找到S6。当发生单个或双重错误时，进行错误校正16，并且S5和S6均为0; 并且开关19通过或门41将误差校正部分16的输出传送到输出端子7。

5. 发明专利

JP5340286B2 Erasure correction coding apparatus and erasure correction coding method 有权
公开(公告)号：JP5340286B2
公开(公告)日：2013-11-13
申请号：JP2010518930
申请日：2009-07-02
申请人：パナソニック株式会社
发明人：豊村上 , 周太岡村
IPC分类号： H03M13/19
CPC分类号： H04L1/0041 , H03M13/1154 , H03M13/17 , H03M13/2703 , H03M13/2707 , H03M13/353 , H03M13/356 , H03M13/373 , H03M13/3761 , H03M13/6306 , H03M13/6356 , H04L1/00 , H04L1/08
摘要： A loss correction encoding device having an improved capability of loss correction using LDPC-CC is disclosed. In the loss correction encoding device (120), a rearranging unit (122) rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q-1) / q of a check polynomial of the loss correction code used in a loss correction encoding unit (123). Specifically, the rearranging unit (122) rearranges the information data in such a way that continuous Kmax × (q-1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit (122) distributes the information data to information blocks from n information packets ( n satisfies formula (1)). Kmax × q - 1 ‰¤ n

6. 发明专利

JP2011514743A Phased burst error in the received symbol sequence, erasure, symbol error, and a method and system for detecting and correcting bit errors 审中-公开
公开(公告)号：JP2011514743A
公开(公告)日：2011-05-06
申请号：JP2010546734
申请日：2008-03-03
申请人：ヒューレット−パッカードデベロップメントカンパニーエル.ピー.
发明人：ヴォントベル，パスカル，オー , ロス，ロン，エム
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G11C7/1006 , G11C2029/0411 , H03M13/134 , H03M13/154 , H03M13/17 , H03M13/2906
摘要：本発明の実施形態は、エラーまたは消失のフェーズドバースト並びに他のシンボルエラー及びビットエラーを訂正するのに適したECCベースの符号化及び復号化方式を含む。本発明の１実施形態を表す符号化及び復号化方式の各々は、２つ以上のコンポーネントエラー訂正コード及び写像関数f(・)から構成される。本発明の実施形態を表すコンポジットエラー訂正コードは、単一ビットエラー及びシンボルエラーに加えて、コンポーネントコードだけの場合よりも長いフェーズドバーストエラーまたは多くの消失を訂正することができ、他のビットエラー及びシンボルエラーと結合したシンボルエラー及び消失のフェーズドバーストを訂正するためにこれまでに開発されているECCベースの符号化及び復号化方式よりも効率が良い。
【選択図】図１５Ａ

7. 发明专利

JP2011028795A Error correcting apparatus, method of controlling memory of the same, and optical disk recording and playback apparatus 有权
标题翻译：错误校正装置，控制其记忆的方法和光盘记录和播放装置
公开(公告)号：JP2011028795A
公开(公告)日：2011-02-10
申请号：JP2009171467
申请日：2009-07-22
申请人： Sony Corp , ソニー株式会社
发明人： YAMADA KAZUHIKO
IPC分类号： G11B20/18 , G06F11/08 , H03M13/29
CPC分类号： H03M13/2954 , G11B20/18 , G11B2020/1846 , G11B2220/2541 , H03M13/1515 , H03M13/17 , H03M13/356 , H03M13/6505
摘要： PROBLEM TO BE SOLVED: To reduce increment of memory capacity used during error correction. SOLUTION: An error correcting apparatus (35) includes a memory (351) and an error correcting unit (357). The memory performs first operation and second operation alternatively. In the first operation, a plurality of frame data possessed by first block data already stored are read out in the row direction sequentially, and a plurality of frame data possessed by second block data are stored sequentially in the row direction into a free area after read-out linking with read-out. In the second operation, a plurality of frame data possessed by second block data stored in the first operation are read out in the column direction sequentially, and a plurality of frame data possessed by the first block data are stored sequentially in the row direction into the free area after read-out linking with read-out. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少纠错期间使用的存储容量的增加。解决方案：纠错装置（35）包括存储器（351）和错误校正单元（357）。存储器交替地执行第一操作和第二操作。在第一操作中，已经存储的第一块数据所拥有的多个帧数据在行方向上被顺序地读出，并且由第二块数据拥有的多个帧数据在行方向上被顺序地存储到读取之后的空闲区域 - 与读出连接。在第二操作中，顺序地在列方向上读出存储在第一操作中的第二块数据所拥有的多个帧数据，并且将由第一块数据拥有的多个帧数据沿行方向顺序地存储到读取后的空闲区域与读出连接。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2009163869A Method and device for recording multiword information 有权
标题翻译：用于记录多媒体信息的方法和装置
公开(公告)号：JP2009163869A
公开(公告)日：2009-07-23
申请号：JP2009043538
申请日：2009-02-26
申请人： Mediatek Inc , メディアテックインコーポレイテッドMediatek Inc.
发明人： WU WEN-YI , LIN LI-LIEN , SHIEH JIA-HORNG
IPC分类号： G11B20/18 , G06F11/10
CPC分类号： G11B20/18 , G11B20/1809 , G11B2020/1288 , G11B2220/2541 , H03M13/17 , H03M13/27 , H03M13/29
摘要： PROBLEM TO BE SOLVED: To provide a method for recording multiword information. SOLUTION: Firstly, ECC including high protective codewords, e.g. BIS, and low protective codewords, e.g. LDC is provided. Then, the high protective codewords and the low protective codewords are stored into a first memory, e.g. DRAM. Then, the high protective codewords are decoded to generated high protective word erasure indicators showing whether decoding errors occur. Then, the high protective word erasure indicators are stored into a second memory, e.g. SRAM. Then, the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于记录多字信息的方法。解决方案：首先，ECC包括高保护码字，例如 BIS和低保护码字，例如。提供LDC。然后，高保护码字和低保护码字被存储到第一存储器中，例如， DRAM。然后，对高保护码字进行解码以产生高保护字擦除指示器，显示是否发生解码错误。然后，高保护字擦除指示符被存储到第二存储器中，例如， SRAM。然后，低保护码字被解码。同时，通过在多字信息簇中找到靠近低保护码字的高保护码字，并查找靠近低保护码字的高保护码字的高保护字擦除指示符，标记出低保护码字的擦除位。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JPWO2007055150A1 通信装置、送信機、受信機および誤り訂正光通信システム审中-公开
公开(公告)号：JPWO2007055150A1
公开(公告)日：2009-04-30
申请号：JP2007544113
申请日：2006-11-02
申请人：三菱電機株式会社
发明人：水落　隆司 , 隆司水落 , 巨生鈴木 , 巨生鈴木 , 小崎　成治 , 成治小崎
IPC分类号： H04L1/00 , H03M13/27
CPC分类号： H04L1/0041 , H03M13/1515 , H03M13/17 , H03M13/2707 , H04L1/0071
摘要：本発明にかかる通信装置は、送信部として、情報フレームのビット位置を並べ替えるインタリーバ11と、並べ替え後の情報フレームに対して誤り訂正符号化を行うFECエンコーダ12と、情報フレームの所定位置にFECパリティを挿入して送信信号を生成するセレクタ14と、を備え、受信部として、受信信号から情報フレーム部分とFECパリティ部分とを抽出するセレクタ21と、情報フレーム部分を送信側と同一のルールで並べ替えるインタリーバ22と、誤り訂正パリティ部分に基づいて並べ替え後のビット列の誤りを訂正するFECデコーダ23と、誤り訂正後のビット位置を元に戻して情報フレームを再生するデインタリーバ24と、を備える。

10. 发明专利

JP2007042234A Error detecting code calculation circuit, error detecting code calculation method, and recording device 有权
标题翻译：错误检测代码计算电路，错误检测代码计算方法和记录设备
公开(公告)号：JP2007042234A
公开(公告)日：2007-02-15
申请号：JP2005226705
申请日：2005-08-04
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： ARIYAMA TAKEO
IPC分类号： G11B20/18 , G11B20/10 , G11B20/12
CPC分类号： G11B20/18 , G11B2020/1272 , H03M13/11 , H03M13/17 , H03M13/29 , H03M13/2903 , H03M13/2906
摘要： PROBLEM TO BE SOLVED: To reduce the amount of accesses to a data buffer when error detecting codes for detecting errors of user data are calculated. SOLUTION: This recording device 1 adds EDCs to user data, and transmits them to a scramble circuit in different order from a coding direction Q. Processing data is constituted so as to be last added in order of the direction Q, but constituted so as to be inserted intermediately in the different order. Accordingly, when data with the EDCs are transmitted in different order, first, a EDC generation section 31 calculates an EDC intermediate value from an expected value of a last half part of an even number sector, and secondly, the EDC generation section 34 receives the user data in the different order and calculates a EDC from an expected value of a first half part of the even number sector, and an expected value and an EDC intermediate value of an odd number sector. The expected value has the number of the same bits as the data with the EDCs, and is an error detection value of a code sequence in which only corresponding bits when the order of the direction Q is matched are set to 1, and others are set to 0. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：计算用于检测用户数据错误的错误检测代码时，减少对数据缓冲器的访问量。解决方案：该记录装置1将EDC添加到用户数据，并将它们从编码方向Q以不同的顺序发送到加扰电路。处理数据被构成为以方向Q的顺序最后添加，但构成以便以不同的顺序中间插入。因此，当以不同顺序发送具有EDC的数据时，首先，EDC生成部31根据偶数扇区的后半部分的期望值计算EDC中间值，其次，EDC生成部34接收用户数据，并根据偶数扇区的前半部分的期望值和奇数扇区的期望值和EDC中间值计算EDC。期望值具有与EDC的数据相同的位的数量，并且是当方向Q的顺序匹配时仅对应的位被设置为1的代码序列的错误检测值，并且其他被设置版权所有（C）2007，JPO＆INPIT

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