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JP2002374175A Pattern generating method for burst error and detection /correction apparatus for burst error and byte error 有权
标题翻译：用于BURST错误和字节错误的BURST错误和检测/校正装置的模式生成方法
公开(公告)号：JP2002374175A
公开(公告)日：2002-12-26
申请号：JP2001180455
申请日：2001-06-14
申请人： Fanuc Ltd , Eiji Fujiwara , ファナック株式会社 , 英二藤原
发明人： FUJIWARA EIJI , KINOSHITA JIRO
IPC分类号： G06F11/10 , G11B20/18 , H03M13/17 , H04L1/00
CPC分类号： H03M13/17
摘要： PROBLEM TO BE SOLVED: To detect burst errors and byte errors in reception information, and to correct them in parallel.
SOLUTION: A syndrome S is determined from reception information D and a parity inspection matrix for correcting a burst error, having a length up to b bits. the syndrome S is inputted into burst error pattern generating circuits 2-1 through 2-p which overlap by b-1 bits with each other, with each having information framework of 2b-bit length. If the burst error is contained completely in the framework of one of the circuits 2-1 through 2-p, this burst error pattern is outputted. An error pattern calculating circuit 3 takes logical OR with an overlapping part from the outputs of the circuits 2-1 through 2-p. Exclusive OR of the output of the circuit 3 and the information D is taken, to obtain a correction information DS. Thus, burst error in the information D can be detected and corrected.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：检测接收信息中的突发错误和字节错误，并并行纠正。解决方案：从接收信息D和用于校正长度高达b比特的突发错误的奇偶校验矩阵确定校验子S。校正子S被输入到以b-1比特重叠的突发错误模式生成电路2-1至2-p，每个具有2b位长的信息框架。如果突发错误完全包含在电路2-1至2-p之一的框架中，则输出该突发错误模式。错误模式计算电路3从电路2-1至2-p的输出端与重叠部分进行逻辑或运算。采用电路3的输出和信息D的异或以获得校正信息DS。因此，可以检测和校正信息D中的突发错误。

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