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61. 发明专利

JP2007018693A Temperature dependent self refresh module for memory device 审中-公开
标题翻译：用于存储器件的温度依赖性自激模块
公开(公告)号：JP2007018693A
公开(公告)日：2007-01-25
申请号：JP2006186638
申请日：2006-07-06
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： THWAITE PETER , HOKENMAIER WOLFGANG
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626
摘要： PROBLEM TO BE SOLVED: To reduce power consumption during standby by reducing the fundamental frequency of a self refresh oscillator.
SOLUTION: The self refresh module includes the oscillator constituted so as to supply a first signal having a first frequency, a trimming divider constituted so as to supply a second signal having a second frequency by trimming the first signal, and a temperature sensor constituted so as to supply a temperature signal by sensing the temperature of a memory device. The self refresh module includes a temperature reference table constituted so as to receive the temperature signal and supply a third signal based on the temperature signal, and a temperature divider constituted so as to supply a self refresh pulse based on the second signal and the third signal.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过降低自刷新振荡器的基频来降低待机期间的功耗。解决方案：自刷新模块包括构成为提供具有第一频率的第一信号的振荡器，通过修整第一信号来提供具有第二频率的第二信号的微调分频器，以及温度传感器构成为通过感测存储器件的温度来提供温度信号。自刷新模块包括温度基准表，其构成为接收温度信号并且基于温度信号提供第三信号;以及温度分配器，其构成为基于第二信号和第三信号提供自刷新脉冲。版权所有（C）2007，JPO＆INPIT

62. 发明专利

JP2007013180A Fluid for immersion lithography system 有权
标题翻译：流体力学系统
公开(公告)号：JP2007013180A
公开(公告)日：2007-01-18
申请号：JP2006179810
申请日：2006-06-29
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： GOODWIN FRANCIS , MARTINICK BRIAN , BRANDL STEFAN
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： G03F7/2041 , G03F7/70341
摘要： PROBLEM TO BE SOLVED: To provide a fluid for use in an immersion lithography system. SOLUTION: A resistivity-altering substance is introduced into a fluid so as to make the fluid conductive. The fluid 230 is then positioned between the immersion head 220 of a projection lens system and a semiconductor wafer 202 during an exposure process. Because the fluid 230 is conductive, electrostatic energy that is generated while the semiconductor wafer moves with respect to the projection lens system during the exposure process is discharged through the conductive fluid, thereby preventing damage to the immersion head 220 of the projection lens system, the semiconductor wafer 202, and sensors in a stage supporting the semiconductor wafer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于浸没式光刻系统中的流体。解决方案：将电阻率变化物质引入流体中以使流体导电。然后在曝光过程中将流体230定位在投影透镜系统的浸没头220和半导体晶片202之间。由于流体230是导电的，所以在曝光过程中半导体晶片相对于投影透镜系统移动时产生的静电能量通过导电流体被排出，从而防止对投影透镜系统的浸没头220的损坏，半导体晶片202以及支撑半导体晶片的台阶中的传感器。版权所有（C）2007，JPO＆INPIT

63. 发明专利

JP2009111391A Integrated circuit including doped semiconductor line having conductive cladding 审中-公开
标题翻译：集成电路，包括具有导电封接的二极管半导体线
公开(公告)号：JP2009111391A
公开(公告)日：2009-05-21
申请号：JP2008278509
申请日：2008-10-29
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： ULRICH KLOSTERMANN , SCHWERIN ULRIKE GRUENING VON , KREUPL FRANZ
IPC分类号： H01L27/105 , H01L21/3205 , H01L23/52 , H01L27/10 , H01L45/00
CPC分类号： H01L27/228 , H01L21/743 , H01L21/76224 , H01L27/224 , H01L27/2409 , H01L27/2436 , H01L45/06
摘要： PROBLEM TO BE SOLVED: To provide configuration of a semiconductor line for reducing the voltage drop in wiring and power consumption, by reducing the resistivity of wiring for selecting memory cells of a memory cell array. SOLUTION: An integrated circuit includes an array of the respective memory cells and the respectively doped semiconductor lines 202, formed in a semiconductor substrate. The doped semiconductor line 202 is coupled with a row of memory cells. The integrated circuit includes a conductive cladding part 203, which is in contact with the respective doped semiconductor lines 202. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过降低用于选择存储单元阵列的存储单元的布线的电阻率，提供用于减少布线中的电压降和电力消耗的半导体线路的配置。解决方案：集成电路包括形成在半导体衬底中的相应存储单元阵列和分别掺杂的半导体管线202。掺杂半导体管线202与一行存储器单元耦合。集成电路包括与相应的掺杂半导体线路202接触的导电覆层部分203.（C）2009，JPO＆INPIT

64. 发明专利

JP2008277831A Probing apparatus and operation method therefor 审中-公开
标题翻译：探测器及其操作方法
公开(公告)号：JP2008277831A
公开(公告)日：2008-11-13
申请号：JP2008118812
申请日：2008-04-30
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： JANUSCH PETER
IPC分类号： H01L21/66 , G01R1/06 , G01R31/28
CPC分类号： G01R31/286 , G01R31/2874
摘要： PROBLEM TO BE SOLVED: To provide a probing apparatus that is capable of reducing the time period (maximum of five hours) when the production test is unable to be carried out by using adaptation of the probing apparatus, and to provide an operation method for such a probing apparatus.
SOLUTION: An operation method for the probing apparatus has a step to control the temperature of the probing apparatus at least partially. Another operation method for the probing apparatus has a step for generating and transferring the thermal energy between a heat-exchange means and at least one member on the probing apparatus, wherein a generation step, a transfer step, and a generation and transfer step for the thermal energy are controlled. The probing apparatus includes, at least one heat-exchange element 24, which is arranged in a spatial relation relative to at least one probe fixture support 22 and affect the temperature of the probe fixture support.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种探测装置，该探测装置能够通过使用探测装置的适应性而不能进行生产测试而缩短时间段（最多5小时），并提供操作这种探测装置的方法。解决方案：用于探测装置的操作方法具有至少部分地控制探测装置的温度的步骤。用于探测装置的另一种操作方法具有在热交换装置和探测装置上的至少一个构件之间产生和传递热能的步骤，其中生成步骤，转移步骤以及生成和转移步骤热能被控制。探测装置包括至少一个热交换元件24，该热交换元件24相对于至少一个探针夹具支撑件22以空间关系布置并且影响探针夹具支撑件的温度。版权所有（C）2009，JPO＆INPIT

65. 发明专利

JP2008263201A Integrated circuit with memory cell array and method for forming same 审中-公开
标题翻译：具有存储单元阵列的集成电路及其形成方法
公开(公告)号：JP2008263201A
公开(公告)日：2008-10-30
申请号：JP2008102660
申请日：2008-04-10
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： POPP MARTIN , SCHLOESSER TILL , SCHWERIN ULRIKE GRUENING VON , WEIS ROLF
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit with a memory cell array and a method for forming the same. SOLUTION: There are provided each bit line 61 extended along a first direction 62, each word line 60 extended along a second direction 63 crossing the first direction 62 substantially perpendicularly, each active region 40, and each bit line contact 57. Each bit line contact 57 is arranged in each column extended along the second direction 63 and in each row extended along the first direction 62. A distance dL between bit lines 61 adjacent each other and a distance dC parallel to the first direction 62 between bit line contacts 57 adjacent each other satisfy a relation 1/2.25≤dL/dC≤1/1.75. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有存储单元阵列的集成电路及其形成方法。解决方案：提供沿着第一方向62延伸的每个位线61，每条字线60沿着基本上垂直于第一方向62的第二方向63延伸，每个有源区40和每个位线接触57。位线接触件57布置在沿着第二方向63延伸的每列中，并且沿着第一方向62延伸的每列中。彼此相邻的位线61之间的距离dL和与位线触点之间的第一方向62平行的距离dC 57相互满足关系1 /2.25≤dL/dC≤1/ 1.75。版权所有（C）2009，JPO＆INPIT

66. 发明专利

JP2008118108A Information storage element and method of manufacturing the same 审中-公开
标题翻译：信息存储元件及其制造方法
公开(公告)号：JP2008118108A
公开(公告)日：2008-05-22
申请号：JP2007212625
申请日：2007-08-17
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： UFERT KLAUS DIETER
IPC分类号： H01L27/10 , C01B31/02 , H01L45/00 , H01L49/00 , H01L51/05 , H01L51/30 , H01L51/40
摘要： PROBLEM TO BE SOLVED: To provide an information storage element of which the expandability and the manufacturing cost have been improved. SOLUTION: On a silicon substrate 401, a lower contact 402 electrically connected to a word line is deposited, a carbon storage material 403 including hexagonally bonded carbon and tetrahedrally bonded carbon on an upper surface of the lower contact 402 is provided, and upper contacts 404 electrically connected to a bit line are deposited on the carbon storage material 403. This element is constituted so as to store information by changing ratio of the hexagonally bonded carbon and tetrahedrally bonded carbon. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供可扩展性和制造成本提高的信息存储元件。解决方案：在硅衬底401上沉积电连接到字线的下接触件402，在下接触件402的上表面上提供包括六边形接合的碳和四面结合碳的碳储存材料403，并且电连接到位线的上触点404被沉积在碳储存材料403上。该元件构成为通过改变六角形键合的碳和四面体键合碳的比例来存储信息。版权所有（C）2008，JPO＆INPIT

67. 发明专利

JP2008072106A Memory cell array and method of forming the memory cell array 审中-公开
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：JP2008072106A
公开(公告)日：2008-03-27
申请号：JP2007222134
申请日：2007-08-29
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： HEINECK LARS , POPP MARTIN
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/10867 , H01L27/10876 , H01L27/10882 , H01L27/10891
摘要： PROBLEM TO BE SOLVED: To provide a DRAM memory cell array with a narrowed memory cell region. SOLUTION: Each memory cell includes a storage capacitor 3, an access transistor 16, a plurality of bit lines 2 oriented in a first direction, a plurality of word lines 8 oriented in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate 1 with a surface, and a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction. Each of the access transistors is partially formed in the active areas and electrically couples corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode 19 of each of the access transistors is connected with a corresponding word line 8, a capacitor dielectric 38 of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有变窄的存储单元区域的DRAM存储单元阵列。解决方案：每个存储单元包括存储电容器3，存取晶体管16，沿第一方向定向的多个位线2，沿第二方向定向的多个字线8，第二方向垂直于第一方向，具有表面的半导体衬底1和形成在半导体衬底中的多个有源区，每个有源区沿第二方向延伸。每个存取晶体管部分地形成在有源区域中并将对应的存储电容器电耦合到对应的位线，其中每个存取晶体管的栅极电极19与对应的字线8，电容器电介质38 的存储电容器的相对介电常数大于8，并且字线设置在位线上方。版权所有（C）2008，JPO＆INPIT

68. 发明专利

JP2008016855A Semiconductor device with laminated chip and method for manufacturing it 审中-公开
标题翻译：具有层压芯片的半导体器件及其制造方法
公开(公告)号：JP2008016855A
公开(公告)日：2008-01-24
申请号：JP2007178800
申请日：2007-07-06
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： SIMON JUERGEN , HEDLER HARRY
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/90 , H01L21/76898 , H01L23/481 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/83 , H01L25/0652 , H01L25/50 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/0557 , H01L2224/06136 , H01L2224/13009 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/2518 , H01L2224/81141 , H01L2224/81191 , H01L2224/83194 , H01L2224/838 , H01L2224/9201 , H01L2224/9202 , H01L2225/06541 , H01L2225/06593 , H01L2225/06596 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element with a laminated chip in which productivity in manufacturing process is excellent. SOLUTION: The method for manufacturing the semiconductor element consists of: a process of preparing a first semiconductor wafer 8 having a first contact pad 5 in an upper part side; a process of disposing a convex-like contact bump 12 the contact pad 5 of the first semiconductor element 8; a process of preparing a second semiconductor element 15 in which a through hole extends to a lower part from a contact pad 18; and a process of setting the second semiconductor element 15 to be adjacent to the first semiconductor element and arranging the convex-like contact bump 12 in the through hole to be electrically connected to the contact pad 18 of the second semiconductor element 15. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体元件的方法，该半导体元件具有制造工艺的生产率优异的层压芯片。解决方案：制造半导体元件的方法包括：制备在上部侧具有第一接触焊盘5的第一半导体晶片8的工艺; 将凸状接触凸块12设置为第一半导体元件8的接触焊盘5的工序; 制备其中通孔从接触垫18延伸到下部的第二半导体元件15的工艺; 以及将第二半导体元件15设置为与第一半导体元件相邻并且将凸状接触凸块12布置在通孔中以与第二半导体元件15的接触焊盘18电连接的工艺。版权所有（C）2008，JPO＆INPIT

69. 发明专利

JP2008004938A Method for attaching solder to rewiring 审中-公开
标题翻译：将焊接接头重新焊接的方法
公开(公告)号：JP2008004938A
公开(公告)日：2008-01-10
申请号：JP2007159777
申请日：2007-06-18
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： TROVARELLI OCTAVIO , MARTIN REISS , ZIMMERMANN BERND
IPC分类号： H01L23/12
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method for attaching solder to rewiring to minimize costs for manufacturing a solder resist mask. SOLUTION: As for a method for attaching solder to rewiring as metallic conductive rewriting, rewiring 7 is provided with a solder pad 9, and installed on the surface of a semiconductor chip 1. Also, solder 15 is melted on the solder pad. A covering material 11 for preventing the passivation of the rewiring is applied to the solder pad on the metallic surface of the rewiring, and then the surface of the rewiring is passivated, that is, solder resist characteristics are applied to the above mentioned surface in order to the minimize costs for manufacturing a solder resist mask. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于将焊料附着到重新布线的方法，以最小化制造阻焊掩模的成本。解决方案：对于将金属焊接重新布线作为金属导电重写的方法，重新布线7设置有焊盘9，并安装在半导体芯片1的表面上。另外，焊料15在焊盘上熔化。将用于防止重新布线钝化的覆盖材料11施加到重新布线的金属表面上的焊盘上，然后将重新布线的表面钝化，即阻焊特性按顺序施加到上述表面以最小化制造阻焊掩模的成本。版权所有（C）2008，JPO＆INPIT

70. 发明专利

JP2008001989A Sputter deposition apparatus and method 审中-公开
标题翻译：溅射沉积装置和方法
公开(公告)号：JP2008001989A
公开(公告)日：2008-01-10
申请号：JP2007165010
申请日：2007-06-22
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： UFERT KLAUS DIETER
IPC分类号： C23C14/35 , H01L21/363
CPC分类号： H01J37/34 , C23C14/225 , C23C14/352 , C23C14/355 , C23C14/357 , C23C14/50 , H01J37/32678 , H01J37/32706 , H01J37/3405 , H01J37/3438 , H01L45/06 , H01L45/085 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1658
摘要： PROBLEM TO BE SOLVED: To provide a sputter deposition apparatus and a method therefor capable of homogeneously depositing a sputtered material since a light component in the sputtered material is likely deposited in higher concentration than that of a heavy component in the sputtered material.
SOLUTION: A sputter deposition apparatus is provided, including at least one sputter target 2, a first plasma 3, a substrate holder 4, and a further plasma 5. The further plasma 5 is preferably an ECWR plasma. According to an additional embodiment of the invention, an anode 6 is provided between the further plasma 5, and the substrate holder 4. According to a further embodiment, the substrate holder 4 includes a dielectric layer with varying thickness.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够均匀沉积溅射材料的溅射沉积设备及其方法，因为溅射材料中的轻组分可能以比溅射材料中的重组分更高的浓度沉积。解决方案：提供溅射沉积设备，其包括至少一个溅射靶2，第一等离子体3，衬底保持器4和另外的等离子体5.另外的等离子体5优选为ECWR等离子体。根据本发明的另外的实施例，阳极6设置在另外的等离子体5和衬底保持器4之间。根据另一实施例，衬底保持器4包括具有变化厚度的电介质层。版权所有（C）2008，JPO＆INPIT

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