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51. 发明专利

JPS61206314A TIMING GENERATING CIRCUIT 失效
公开(公告)号：JPS61206314A
公开(公告)日：1986-09-12
申请号：JP4637885
申请日：1985-03-11
申请人： CANON KK
发明人： TAKAO KOJI
IPC分类号： H03K5/15 , H03K5/156 , H03K23/54 , H03K23/64 , H03K23/66
摘要： PURPOSE:To obtain a circuit with ease of timing design and high expansion by using a PLA for a selection circuit selecting >=1 output of an FF circuit constituting a ring counter and selecting the input to a logical gate circuit by the selection circuit externally in a way of program. CONSTITUTION:As the selection circuit changing the connection required for various timing signals, a PLA (programmable logic array) is used. In figure, the mark X is a part for connection command externally. The number of stages of the ring counters deciding the period of the generated timing signal depends on it to which stage output of the ring counter the input to an inverting circuit 38 is connected. Further, as to the time position of the timing waveform and the pulse width, they depend on it to which stage output of the ring counter the input to exclusive OR circuits 31-33 is connected. Thus the same PLA device is used to obtain a desired timing signal by making the connection of Xmark programmable.

52. 发明专利

JPS61206311A TIMING GENERATING CIRCUIT 失效
公开(公告)号：JPS61206311A
公开(公告)日：1986-09-12
申请号：JP4637585
申请日：1985-03-11
申请人： CANON KK
发明人： TAKAO KOJI
IPC分类号： H03K5/15 , G06F1/06 , H03K5/156 , H03K23/54 , H03K23/64 , H03K23/66
摘要： PURPOSE:To obtain a circuit generating a timing inverted at each period by adopting an odd number of input signals to a logical gate circuit in a timing generating circuit using a ring counter. CONSTITUTION:Outputs Q7, Q9 of stages 1, 3 of a ring counter are used as inputs to an exclusive OR circuit 1. Thus, when the state of the outputs Q7, Q9 are not equal, the output of the exclusive OR goes to logical '1'. When the outputs Q7, Q9 are not the same, that is, when the boundary between logical '0' and logical '1' reaches up to the output Q9, the output is inverted to logical '0'. Thus, the exclusive OR output goes to logical '1' for the time of stage difference between the 1st stage Q4d7 and the 3rd stage Q9, that is, 3-1=2 clocks' content. Then the same waveform is repeated for the period when the ring counter is circulated, that is, at each 5 clocks.

53. 发明专利

JPS61206310A TIMING GENERATING CIRCUIT 失效
公开(公告)号：JPS61206310A
公开(公告)日：1986-09-12
申请号：JP4637485
申请日：1985-03-11
申请人： CANON KK
发明人： TAKAO KOJI
IPC分类号： H03K5/15 , H03K5/156 , H03K23/54 , H03K23/64 , H03K23/66
摘要： PURPOSE:To generate a timing signal with various periods in a semicustom manner with high general-purpose application and expansion by forming a selection circuit into a so-called programmable logic array (PLA) and diciding the operation of the selection circuit in a way of program from the outside of a timing generating circuit. CONSTITUTION:The number of stages of a ring counter deciding the period of the generated timing signal depends on to which stage output of the ring counter the input to an inverter circuit 38 is connected and the said connection marked by X in figure is made programmable to form the timing generating circuit with different period by using the same PLA device. Further, the time position and the pulse width of the timing waveform depend on to which stage output of the ring counter is connected to the input to exclusive OR circuits 31-33 and the connection marked by X in figure is made programmable so as to use the same PLA device to form the timing generating circuit different from the time position of timing and the pulse width.

54. 发明专利

JPS61164331A FREQUENCY DIVIDER 失效
公开(公告)号：JPS61164331A
公开(公告)日：1986-07-25
申请号：JP122586
申请日：1986-01-07
申请人： LIGNES TELEGR & TELEPH SA LTT
发明人： ERITSUKU BORUNIYU , MOORISU NIKERU
IPC分类号： H03K23/00 , H03K23/54 , H03K23/66

55. 发明专利

JPS60180332A FREQUENCY DIVISION CIRCUIT 失效
公开(公告)号：JPS60180332A
公开(公告)日：1985-09-14
申请号：JP3679684
申请日：1984-02-28
申请人： FUJITSU LTD
发明人： OKADA KIMIYOSHI , SUZUKI TERUHIKO , ARAI MASANORI , TSUDA TAKASHI
IPC分类号： H03K23/00 , H03K23/40 , H03K23/54
摘要： PURPOSE:To obtain plural normal frequency division outputs even missing of a clock exists by connecting plural flip-flops delayed at each clock to be frequency-divided in cascade and providing a means delaying only a clock of the 1st stage for a prescribed time when a required output of the next and succeeding stage is fed back to the 1st stage so as to obtain plural desired frequency dividing outputs. CONSTITUTION:A delay circuit DL11 delaying only a clock 10' to a DFF1 by a prescribed time from a clock 10 to DFFs 2, 3 is provided. when a phase difference tA between a feedback data and the clock is smaller than a setup time tsu of the DFF1 in case of the clock 10 not delayed, malfunction takes place. The phase difference between the feedback data and the clock is taken as a tB by using the clock 10' so as to increase it more than the tsu, then the DFF1 is operated normally with a margin. Furthermore, tC, tD represent the phase differences between the data D2, D3 of the DFFs 2, 3 and the clock when the clock 10' of the DFF1 is delayed, increased more than each tsu of the DFFs 2, 3 the same as the case with the tB and the DFFs are operated normally and surely.

56. 发明专利

JPS6036137B2 失效
公开(公告)号：JPS6036137B2
公开(公告)日：1985-08-19
申请号：JP3054379
申请日：1979-03-15
申请人： MOTOROLA INC
发明人： SHIKUN KYU
IPC分类号： H03K23/54 , H03K23/42 , H03K23/66 , H03K23/68

57. 发明专利

JPS60113526A FREQUENCY DIVIDER 失效
公开(公告)号：JPS60113526A
公开(公告)日：1985-06-20
申请号：JP22092283
申请日：1983-11-24
申请人： SUWA SEIKOSHA KK
发明人： YAMADA ICHIROU
IPC分类号： H03K23/54 , H03K3/356
摘要： PURPOSE:To obtain a frequency divider with setting in a simple constitution where just a single transistor is added to a dynamic frequency divider, by permitting a setting action only with the specific timing. CONSTITUTION:A transistor TR102 is connected among a dynamic 1/2 frequency divider consisting of TR1-10, a terminal VC13 and a low level. Then a set signal is applied to the gate of the TR102. When a set terminal 105 is set at a low level, the TR102 is turned off and functions as a normal dynamic frequency divider. A set signal is produced synchronously with the rise of a clock CL. Then the TR102 is turned on when the terminal 105 is set at a high level, and the terminal VC13 is fircibly set at a low level. Thus a terminal VA11 is set at a high level.

58. 发明专利

JPS5945295B2 JPS5945295B2 - 失效
公开(公告)号：JPS5945295B2
公开(公告)日：1984-11-05
申请号：JP11287277
申请日：1977-09-19
申请人： Sanyo Electric Co
发明人： AKYAMA TOORU , OOGISHI TSUTOMU
IPC分类号： H03K23/64 , H03K23/54 , H03K23/66
CPC分类号： H03K23/66

59. 发明专利

JPS5945263B2 JPS5945263B2 - 失效
公开(公告)号：JPS5945263B2
公开(公告)日：1984-11-05
申请号：JP15835176
申请日：1976-12-27
申请人： Tokyo Shibaura Electric Co
发明人： TANAKA NORISHIGE , SUZUKI YASOJI
IPC分类号： H03K23/52 , H03K23/42 , H03K23/54
CPC分类号： H03K23/42

60. 发明专利

JPS5945262B2 JPS5945262B2 - 失效
公开(公告)号：JPS5945262B2
公开(公告)日：1984-11-05
申请号：JP6647676
申请日：1976-06-09
申请人： Tokyo Shibaura Electric Co
发明人： KATAKURA MASAYUKI
IPC分类号： H03K3/72 , H03K3/2885 , H03K5/15 , H03K5/151 , H03K23/52 , H03K23/54
CPC分类号： H03K3/2885

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