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52. 发明专利

JP5305543B2 A method and apparatus for calibrating the writing timing of the memory system 有权
公开(公告)号：JP5305543B2
公开(公告)日：2013-10-02
申请号：JP2010539527
申请日：2008-03-03
申请人：ラムバス・インコーポレーテッド
发明人：ギオバンニニ，トマス , グプタ，アロク , シャエファー，イアン , ウー，スティーブン，シー．
IPC分类号： G06F12/00 , G11C11/401 , G11C11/4076
CPC分类号： G11C11/4076 , G06F1/08 , G06F3/0629 , G06F3/0634 , G06F5/06 , G06F12/0646 , G06F13/1689 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/409 , G11C11/4096 , G11C2207/2254
摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

53. 发明专利

JP2012216652A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012216652A
公开(公告)日：2012-11-08
申请号：JP2011080393
申请日：2011-03-31
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KONDO TSUTOMU
IPC分类号： H01L27/108 , G11C5/00 , H01L21/8242 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/10
CPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C11/4063 , G11C11/4076 , H01L2224/16145
摘要： PROBLEM TO BE SOLVED: To sufficiently ensure the effective width (window width) of read data in a stacked semiconductor device.SOLUTION: A semiconductor device comprises a plurality of stacked core chips CC0 to CC7 and an interface chip IF controlling the core chips. Each of the core chips comprises a memory cell array 70, a through electrode TSV1 for data, and an output circuit RBUFO that outputs read data read from the memory cell array 70 to the through electrode TSV1 for data. The through electrodes TSV1 for data provided in respective core chips are commonly connected to one another, and the output circuits RBUFO provided in respective core chips are activated in response to a read clock signal RCLKDD supplied from the interface chip IF. As a result, the conflict of the read data on a data bus does not occur even if variation in operating speed of each core chip exists.
摘要翻译：要解决的问题：充分确保层叠半导体器件中读取数据的有效宽度（窗口宽度）。解决方案：半导体器件包括多个堆叠的核心芯片CC0至CC7以及控制芯片的接口芯片IF。每个核心芯片包括存储单元阵列70，用于数据的通孔TSV1，以及输出电路RBUFO，其将从存储单元阵列70读取的读取数据输出到贯穿电极TSV1用于数据。用于各个核心芯片中提供的数据的贯通电极TSV1彼此共同连接，并且响应于从接口芯片IF提供的读取时钟信号RCLKDD而激活设置在各个核心芯片中的输出电路RBUFO。结果，即使存在每个核心芯片的操作速度的变化，数据总线上的读取数据的冲突也不会发生。版权所有（C）2013，JPO＆INPIT

54. 发明专利

JP5014446B2 Method and apparatus for adjusting the memory operations from the memory component that has been variously placed 有权
标题翻译：空值
公开(公告)号：JP5014446B2
公开(公告)日：2012-08-29
申请号：JP2010030473
申请日：2010-02-15
申请人：ラムバス・インコーポレーテッド
发明人：エリー・ケイ・ツァーン , クレイグ・イー・ハンペル , フレデリック・エイ・ウェア , リチャード・イー・ペレゴ
IPC分类号： G06F12/00 , G06F13/16 , G06F13/40 , G06F13/42 , G11C8/00 , G11C11/401 , G11C29/00 , G11C29/02
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.
摘要翻译：特定地址和控制总线以及数据总线（108）连接到存储器控制器（102）和存储器模块（103）。数据总线使用差分信号，符号时间小于特定地址和控制总线符号时间。

55. 发明专利

JP4919767B2 Semiconductor memory device 有权
公开(公告)号：JP4919767B2
公开(公告)日：2012-04-18
申请号：JP2006305672
申请日：2006-11-10
申请人：株式会社東芝
发明人：晃寛仁田山 , 澤隆大 , 本毅司浜 , 田良福 , 智彰篠 , 地英明青
IPC分类号： H01L27/108 , G11C11/404 , H01L21/8242
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841

56. 发明专利

JP2011166131A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011166131A
公开(公告)日：2011-08-25
申请号：JP2011005456
申请日：2011-01-14
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： YAMAZAKI SHUNPEI , KOYAMA JUN , KATO KIYOSHI
IPC分类号： H01L21/8242 , G11C11/405 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： G11C11/409 , G11C11/404 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in new structure capable of retaining storage content, even in a situation where no power is being supplied which does not limit the number of write operations. SOLUTION: The semiconductor device includes a source line; a bit line; a first signal line; a second signal line; a word line; a memory cell connected between the source line and the bit line; a first driver circuit electrically connected to the bit line; a second driver circuit electrically connected to the first signal line; a third driver circuit electrically connected to the second signal line; and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is constituted of a semiconductor material which is other than an oxide semiconductor, and the second transistor is constituted of an oxide semiconductor material. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使在不限制写入次数的情况下，即使在不提供电力的情况下，也能够提供能够保持存储内容的新结构的半导体器件。解决方案：半导体器件包括源极线; 有点线第一条信号线第二信号线; 字线连接在源极线和位线之间的存储单元; 电连接到位线的第一驱动电路; 电连接到第一信号线的第二驱动电路; 电连接到第二信号线的第三驱动电路; 以及电连接到字线和源极线的第四驱动电路。第一晶体管由不同于氧化物半导体的半导体材料构成，第二晶体管由氧化物半导体材料构成。版权所有（C）2011，JPO＆INPIT

57. 发明专利

JP2011066050A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011066050A
公开(公告)日：2011-03-31
申请号：JP2009213112
申请日：2009-09-15
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKEDA HIROMASA , ISA SATOSHI , KOBAYASHI KATSUTARO , KATAGIRI MITSUAKI
IPC分类号： H01L27/10 , G11C11/401 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/02 , G11C5/06 , G11C11/409 , G11C2207/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents malfunction due to noise generated by variation in sense amplifier ground potential. SOLUTION: The semiconductor device has: a pad for the sense amplifier ground potential, as an electrode pad for supplying the ground potential to a sense amplifier; a first conductive line, connected to the pad for the sense amplifier ground potential; and a second conductive line, connected to an electrode pad shortest in distance to the pad for the sense amplifier ground potential in a plurality of electrode pads included in a pad array. Here, the second conductive line is extended to the opposite side of the first conductive line with reference to the pad array. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止由于读出放大器接地电位变化而产生的噪声的故障的半导体器件。解决方案：半导体器件具有：用于读出放大器接地电位的焊盘，作为用于向读出放大器提供接地电位的电极焊盘; 第一导线，连接到用于读出放大器接地电位的焊盘; 以及第二导电线，其连接到电极焊盘的最远距离的焊盘，用于焊盘阵列中包括的多个电极焊盘中的读出放大器接地电位。这里，第二导线相对于焊盘阵列延伸到第一导线的相对侧。版权所有（C）2011，JPO＆INPIT

58. 发明专利

JP4569915B2 Semiconductor memory device 有权
公开(公告)号：JP4569915B2
公开(公告)日：2010-10-27
申请号：JP2000245263
申请日：2000-08-11
申请人：エルピーダメモリ株式会社
发明人：保彦高橋
IPC分类号： G11C11/407 , G11C7/22 , G11C8/12 , G11C11/401 , G11C11/409 , G11C11/4096
CPC分类号： G11C7/22 , G11C8/12 , G11C11/409 , G11C2207/2281 , G11C2207/229

59. 发明专利

JP4253097B2 Semiconductor memory device and a method of reading data 有权
公开(公告)号：JP4253097B2
公开(公告)日：2009-04-08
申请号：JP37353199
申请日：1999-12-28
申请人：東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人：成夫大島 , 信夫渡辺
IPC分类号： G11C11/407 , G11C11/4076 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/409
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/409

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