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51. 发明专利

JPS58169965A SOLID-STATE IMAGE PICKUP DEVICE 失效
公开(公告)号：JPS58169965A
公开(公告)日：1983-10-06
申请号：JP5121582
申请日：1982-03-31
申请人： HITACHI LTD
发明人： OOBA SHINYA , ANDOU HARUHISA , NAKAI MASAAKI , OZAKI TOSHIBUMI , SEKI KOUICHI , TAKAHASHI KENJI , AKIYAMA TOSHIYUKI , TAKEMOTO KAYAO , IMAIDE TAKUYA , OKUDA AKIHIDE , KUBO SEIJI
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/365 , H04N5/372
摘要： PURPOSE:To reduce fixed pattern noises and thus obtain a high sensibility by a method wherein an inversion circuit is provided between each vertical signal line and the gate of a transfer transistor, in a bi-dimensional solid-state image pickup element. CONSTITUTION:The inversion circuit 50 wherein the potential of each vertical signal line 4 is decided as one side input and the other side is connected to a common power source line 51 is provided to each vertical signal line, and thus the output is given to the gate of the transfer FET5. By the addition of the inversion circuit 50 of gain G, the transfer loss of charges is remarkably reduced to 1/(1+G) resulting in the improvement of transfer efficiency, but, when the characteristics of the inversion circuit disperse, the conductances of the transfer FET disperse, and the amount of charges read out within a restricted transfer time differs, accordingly large fixed pattern noises are generated. After bias charges are injected from a CTD (e.g. BCD) 8 into the signal lines 4 through FETs 6, or bias charges stored in capacitors provided in the drains 12 of FETs 12 are injected into the signal lines 4, reading is performed. By this constitution, even when the reference potentials of vertical signals disperse in every array, fixed pattern and random pattern noises remarkably reduce and thus a high sensibility can be obtained, if the reference potentials at the time of emitting excess charges and reading are in a slight difference at each signal line 4.

52. 发明专利

JPS58111371A INPUTTING METHOD FOR CHARGE TRANSFER ELEMENT 失效
公开(公告)号：JPS58111371A
公开(公告)日：1983-07-02
申请号：JP20922081
申请日：1981-12-25
申请人： HITACHI LTD
发明人： NAKAI MASAAKI , OOBA SHINYA , ANDOU HARUHISA , OZAKI TOSHIBUMI , AOKI MASAKAZU , IMAIDE TAKUYA , TAKAHASHI KENJI , AKIYAMA TOSHIYUKI , NAGAHARA SHIYUUSAKU
IPC分类号： H01L29/762 , H01L21/339 , H01L27/10 , H01L29/768
摘要： PURPOSE:To input bias charges under a storage gate at a time, and to magnify the function of the charge transfer element by injecting bias charges into the charge transfer element through a well layer from the substrate side. CONSTITUTION:The charge transfer element consists of an N-type Si substrate 1, the P type well 2, P layers 3, a gate insulating film (SiO2) 4, storage electrodes (poly-Si) 5 and transfer electrodes (poly-Si) 6. When P type well potential WWELL is made 0V, positive voltage phi1M is applied to the storage gate and positive voltage Vsub is applied to the substrate 1, the well of potential is formed to the surface. When the well layer 2 is all depleted, punch-through currents flow between the surface and the substrate 1. Accordingly, charges are injected to a surface channel section, and surface channel potential is brought to Vsub. When the well layer 2 is depleted partially, the surface channel section and the substrate 1 are separated electrically. Later, clocks phi1, phi2 transfer charges in succession.

53. 发明专利

JPS57181156A SEMICONDUCTOT DEVICE 失效
公开(公告)号：JPS57181156A
公开(公告)日：1982-11-08
申请号：JP6527082
申请日：1982-04-21
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： OOBA SHINYA , KUBO SEIJI , TAKEMOTO KAYAO , TANAKA SHIYUUHEI , ANDOU HARUHISA
IPC分类号： H01L27/146 , H04N5/335 , H04N5/357 , H04N5/374
摘要： PURPOSE:To reduce the capacity among a switching gate and output lines by a method wherein electrodes are provided between the switching gate and a source region and between the switching gate and a drain region through an insulating film in a MOS type solid image pickup element and a DC voltage is applied to the electrodes. CONSTITUTION:Electrodes 9 consisting of positive Si are provided on a P type semiconductor substrate 11 between the gate 8 and the n type source region 5 and between the gate 8 and the n type drain region 7 of a switching MOS transistor Ts composing a solid image pickup element through an insulating layer 10. With a DC voltage applied to the electrodes 9, the capacity Cp1, Cp2 between the switching gate 8 and output lines 7, 5 become extremly small because the switching gate 8 and the output lines 7, 5 are shielded by the applied DC voltage. Therefore, spike-shaped pulse noises are not superimposed on the signal output line 7 through the capacity Cp1, Cp2 and signal-to-noise ratio can be improved.

54. 发明专利

JPS5775073A Solid image pickup device 失效
标题翻译：固体图像拾取装置
公开(公告)号：JPS5775073A
公开(公告)日：1982-05-11
申请号：JP13552281
申请日：1981-08-31
申请人： Hitachi Ltd
发明人： NAKAI MASAAKI , OOBA SHINYA , ANDOU HARUHISA
IPC分类号： H01L27/146 , H04N5/335 , H04N5/359 , H04N5/374
CPC分类号： H01L27/14654
摘要： PURPOSE:To suppress blooming and increase the storage capacity of a photodiode to improve S/N, by providing a region of a high density surrounding a drain region. CONSTITUTION:A solid image pickup device has a semiconductor substrate 9 of the first conductive type, source and drain regions 121 and 122 formed apart each from other in the surface region of this substrate 9, and a gate electrode 10 provided through an insulating film 12 on the substrate surface between source and drain regions 121 and 122. The source junction is used as a photodiode. A region 13 of the first conductive type having a density higher than density of the impurity of the substrate is provided which surrounds the region 122 and extends to a part under the gate electrode 10 at least.
摘要翻译：目的：通过提供围绕漏极区域的高密度区域，抑制起霜并增加光电二极管的存储容量以改善S / N。构成：固体摄像装置具有第一导电类型的半导体衬底9，在该衬底9的表面区域中彼此分开形成的源极和漏极区域121和122以及通过绝缘膜12提供的栅电极10 在源极和漏极区域121和122之间的衬底表面上。源极结用作光电二极管。提供具有高于衬底的杂质密度的第一导电类型的区域13，其围绕区域122并至少延伸到栅电极10下方的部分。

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