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51. 发明专利

JPS6295870A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6295870A
公开(公告)日：1987-05-02
申请号：JP23514585
申请日：1985-10-23
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI , IKEDA SEIJI , NAKAMURA TORU
IPC分类号： H01L29/78 , H01L21/331 , H01L21/76 , H01L29/72 , H01L29/73
摘要： PURPOSE:To reduce junction capacity and improve propagation delay time by determining depth of element isolation groove formed through the n-type buried layer to a value larger than depth of the interface between the n-type buried layer and p-type substrate from the substrate surface. CONSTITUTION:An element isolation groove is provided through the n-type buried layer 2, the depth of this groove is set larger than the interface of the n-type buried layer 2 from the substrate surface and p-type Si substrate 1, junction capacitance (CTs) is reduced by making small the junction area, propagation delay time (tpa) is set fast and thereby high packing density and high operation rate of high performance bipolar transistor can be realized. As the other embodiment, the electrode 31 is used as the anode of SBD, while the electrode 13 as the cathode thereof. Thereby, the alpha ray resistance can be improved because of the p-type diffusion layer 7. Moreover, when the electrode 13 is used as the anode of SBD and the electrode 14 as the cathode thereof, the transient characteristic of diode can be improved because of small parasitic capacitance.

52. 发明专利

JPS61234066A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61234066A
公开(公告)日：1986-10-18
申请号：JP7422285
申请日：1985-04-10
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE:To remarkably reduce the prescribed area by storing charge directly under a longitudinal transistor. CONSTITUTION:After an N-type epitaxial layer 2, a thermal oxide film 20 and a silicon nitride film 21 are formed on a P-type Si substrate 1, and unnecessary portion is selectively removed to form a partly projected structure. Then, after a polycrystalline silicon 5 is accumulated in a recess, the surface is oxidized to form a silicon dioxide film 7, a polycrystalline silicon 6 is further accumulated in the recess, flattened, and boron is doped in the silicon film 6 by ion implanting technique. Thereafter, when a heat treatment is executed, boron doped in the film 6 is diffused in the layer 2 from the side to form a P-type diffused layer 3, the desired portion of the film 6 is selectively oxidized, silicon dioxide films 7, 8 are formed. Thereafter, an arsenic is doped to form an N-type doped region 4, a contacting hole is formed at the film 8, and A1 electrodes 9-12 are formed.

53. 发明专利

JP2002176190A OPTICAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPTICAL STORING/REPRODUCING DEVICE 失效
公开(公告)号：JP2002176190A
公开(公告)日：2002-06-21
申请号：JP2000373113
申请日：2000-12-07
申请人： HITACHI LTD
发明人： KIMURA SHIGEJI , MAIO KENJI , DOI TAKESHI , TAMAOKI YOICHI , SHIMANO TAKESHI
IPC分类号： H01L27/14 , H01L27/144 , H01L31/02 , H01L31/10
摘要： PROBLEM TO BE SOLVED: To realize high speed reading of an optical information processor by enhancing the sensitivity of a photodiode fabricated on the same SOI substrate as that of other semiconductor circuit devices while enlarging the frequency band. SOLUTION: In order to enlarge the frequency band, the buried layer 502 of a photodiode is buried deep or impurity concentration of the buried layer is reduced. Furthermore, the thickness of an oxide film 401 on the SOI substrate is selected to maximize reflection light.

54. 发明专利

JPH11330473A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11330473A
公开(公告)日：1999-11-30
申请号：JP12839398
申请日：1998-05-12
申请人： HITACHI LTD
发明人： MITANI SHINICHIRO , WAKAHARA YOSHIFUMI , TAMAOKI YOICHI
IPC分类号： H01L27/08 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique which is capable of materializing the high- speed operation of a MISFET made on an SOI board, and prevent the operational failures of the MISFET. SOLUTION: The depletion layer of an n -type semiconductor region 6 and the depletion layer of a p -type semiconductor region 14 are in zero bias contact with an embedded insulating film 2 at all times, by providing this device with a film silicon layer 3 where impurities in low concentration of about 10 cm are implanted between an n -type semiconductor region 6 and an embedded insulating film 2 and between a p -type semiconductor region 14 and the embedded insulating film 2, so that the operation speed of a MISFET can be raised by suppressing the parasitic capacitance low. At the same time, it becomes possible to made the film silicon layer 3 thickness large, and the film silicon layer 3 is provided under an insulating film 4 for element isolation, so that the potential of the film silicon layer 3 can be fixed, and the operation failure of the MISFET caused by potential ripples can be prevented.

55. 发明专利

JPH1154758A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1154758A
公开(公告)日：1999-02-26
申请号：JP20749097
申请日：1997-08-01
申请人： HITACHI LTD
发明人： WAKAHARA YOSHIFUMI , TAMAOKI YOICHI
IPC分类号： H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To enable carriers of reverse polarity generated by impact ionization and staying in a channel region to flow away completely from a MISFET region. SOLUTION: An N-channel MISFET Qn and a P-channel MISFET Qp are formed on an SOI substrate 1 composed of a support substrate 1a, a buried oxide layer 1b, and a silicon layer 1c, a field insulating film 2a is formed on the main surface of the silicon layer 1c so as to reach the buried oxide layer 1b, a field insulating film 2b is formed on the main surface of the silicon layer 1c so as not to reach the oxide layer 1b, and an impurity semiconductor region 14 acting as a back gate is provided to the support substrate 1a which includes an interface region between the buried oxide layer 1b under the field insulating film 2b and the support substrate 1a. The impurity semiconductor region 14 is connected to a back gate electrode 12d formed in an connection hole 11d bored in the interlayer insulating film 10, the field insulating film 2a, and the buried oxide layer 1b, and a negative potential is applied to the semiconductor region 14.

56. 发明专利

JPH113894A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH113894A
公开(公告)日：1999-01-06
申请号：JP15272097
申请日：1997-06-10
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , HASHIMOTO TAKASHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PROBLEM TO BE SOLVED: To make a resistance of an electrode for leading out a base of a vertical bipolar transistor lower, and excellently control the formation of an intrinsic base region. SOLUTION: In a double layer polycrystal silicon structure npn transistor 4 which has a collector region 4C consisting of a collector buried layer 4C1, an intrinsic collector region 4C2 and a collector lead-out layer 4C3, a base region 4B consisting of an intrinsic base region 4B1 and an external base region 4B2 formed on the perimeter thereof, and an emitter region 4E, and wherein an emitter lead-out electrode 8E connected to the emitter region 4E and a base lead-out electrode 8B connected to the external base region 4B2 are formed of polycrystal silicon films, the base lead-out electrode 8B consists of a first electrode layer 8B1 and a second electrode layer 8B2 formed thereon, and boron of about 5×10 to 1×10 /cm is introduced in the second electrode layer 8B2, and an impurity is not positively introduced in the first electrode layer 8B1 when it deposited to make it a nondoped layer.

57. 发明专利

JPH10189978A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10189978A
公开(公告)日：1998-07-21
申请号：JP34176696
申请日：1996-12-20
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , IKEDA TAKAHIDE , WAKAHARA YOSHIFUMI , HORIUCHI KATSUTADA , HIGUCHI HISAYUKI
IPC分类号： H01L27/08 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique which improves reliability of a semiconductor integrated circuit device with an MISFET, formed in an SOI board. SOLUTION: A 0.05 to 0.2μm-thick thin film silicon layer 3 with an impurity concentration of 10 /cm or more is formed between an LOCOS oxide film 4 and a embedded oxide film 2. Since minority carriers generated in a channel region thereby diffuse through the thin-film silicon layer 3 below the LOCOS oxide film 4, change in a threshold voltage of an MISFET by storage of the minority carriers can be restrained.

58. 发明专利

JPH08162470A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08162470A
公开(公告)日：1996-06-21
申请号：JP29823394
申请日：1994-12-01
申请人： HITACHI LTD
发明人： KUMAUCHI TAKAHIRO , HASHIMOTO TAKASHI , KASAHARA OSAMU , YAMAMOTO TOMOSHI , TAMAOKI YOICHI , SHIBA TAKEO , UCHINO TAKASHI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L29/165 , H01L29/732 , H01L29/737
摘要： PURPOSE: To lower the resistance in a semiconductor region excluding an emitter region in the state of realizing a shallow junction in the case of using phosphorus as doping element for the emitter electrode. CONSTITUTION: When forming an emitter electrode 24, after depositing phosphorus doped amorphous silicon film, the amorphous silicon is modified to polycrystalline silicon as well as the phosphorus in the amorphous silicon film is diffused to epitaxial layer 3E side to form an epitxial region by low temperature annealing at about 600 deg.C-750 deg.C and then the activity factor of impurities such as semiconductor regions 15p1, 15p2, 15n1, 15n2, etc., of a base element 18a1 or MOS.EFT can be improved by high temperature by a short time annealing process at about 900 deg.C-950 deg.C.

59. 发明专利

JPH0682675B2 失效
公开(公告)号：JPH0682675B2
公开(公告)日：1994-10-19
申请号：JP9360985
申请日：1985-05-02
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , SAGARA KAZUHIKO , SAKAI YOSHIO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732

60. 发明专利

JPH05343627A 失效
公开(公告)号：JPH05343627A
公开(公告)日：1993-12-24
申请号：JP18984091
申请日：1991-07-30
申请人： HITACHI LTD
发明人： SHIBA TAKEO , TAMAOKI YOICHI , ONOUCHI YUKIHIRO , NAKAMURA TORU , SAITO MASAYOSHI
IPC分类号： H01L21/8249 , H01L27/06
摘要： PURPOSE:To facilitate high-level integration and high-speed operation of a semiconductor integrated circuit in which field-effect transistors and high-speed bipolar transistors are arranged on the same semiconductor substrate. CONSTITUTION:The source/drain electrodes of field-effect transistors and the base electrodes of bipolar transistors have structures including two or more layers composed of silicon layers 14 and metal or metal silicide films 15. The width and the interval of the electrodes are determined in a self-alignment manner. When the connection of the electrodes is necessary, the electrodes are directly connected with each other. Thereby the arrangement interval of the field-effect transistors and the bipolar transistor is decreased, and the series resistance between electrodes can be reduced, so that high level integration and high speed operation of the semiconductor integrated circuit using the above transistors are facilitated.

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