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1. 发明专利

JP2003051551A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003051551A
公开(公告)日：2003-02-21
申请号：JP2001235765
申请日：2001-08-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYAMOTO MASABUMI , WAKAHARA YOSHIFUMI
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To realize increase of operating current and reduction of junction capacitance caused by substrate floating without using an expensive SOI substrate, and solve the problems of thermal resistance and crystal defect which are the defects on an SOI substrate.
SOLUTION: An N (P) well NWL (PML) is arranged between a P (N) semiconductor region PA (PN) in which an N (P) channel MISFET Qn (Qp) is arranged and a semiconductor substrate IS. As a result, the P (N) semiconductor region PA (PN) is electrically isolated from the semiconductor substrate IS.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：在不使用昂贵的SOI衬底的情况下实现衬底浮动引起的工作电流的增加和结电容的减少，并且解决作为SOI衬底上的缺陷的热阻和晶体缺陷的问题。解决方案：N（P）阱NWL（PML）布置在其中布置N（P）沟道MISFET Qn（Qp）的半导体区域PA（PN）和半导体衬底IS之间。结果，P（N）半导体区域PA（PN）与半导体衬底IS电隔离。

2. 发明专利

JP2002198529A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002198529A
公开(公告)日：2002-07-12
申请号：JP2001219666
申请日：2001-07-19
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , ONOUCHI YUKIHIRO , ONISHI KAZUHIRO , WAKAHARA YOSHIFUMI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/10 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique for inhibiting variation in a threshold voltage, and for increasing switching speed in a short-channel MISFET. SOLUTION: On the entire surface of a substrate 1 below the channel region of the MISFET, p-type impurity layers 7 and 8 are formed, thus inhibiting the variation in the threshold voltage as compared with a case where a punch- through-stopper layer with a pocket structure is formed. In this case, the p-type impurity layers 7 and 8 have first and second peaks, respectively, in an impurity concentration distribution having a function for preventing punch through. Additionally, the width of a controllable depletion layer becomes relatively large, thus reducing a subthreshold coefficient, and hence preventing the drop of the threshold voltage for increasing the switching speed in the MISFET.

3. 发明专利

JP2000277638A SEMICONDUCTOR DEVICE AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JP2000277638A
公开(公告)日：2000-10-06
申请号：JP7890799
申请日：1999-03-24
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , WAKAHARA YOSHIFUMI
IPC分类号： H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L27/08 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a device constituted of thickness of the silicon layer of a bipolar part or a metal insulator semiconductor field effect transistor MISFET part of the thickness suitable for the device structure, and to provide a flat device structure having no difference in level in the boundary area, and a method for manufacturing the device. SOLUTION: A silicon oxide film is formed on a substrate, having a silicon layer 3 (SOI layer) in a thin-film thickness suitable for the formation of a fully depleted type MISFET, and then an opening 5 is formed. A sidewall 6 constituted of an insulator is formed on the sidewall of the opening 5, and then a single crystal silicon film 8 which is an epitaxial growth film is formed in the opening 5 by using a selective epitaxial growing method. Then, a CMP method is executed on the silicon oxide film on the silicon layer 3, the sidewall 6, and the single crystal silicon film 8 so that the silicon oxide film is removed and flattened. Afterwards, the MISFET is formed on the silicon layer 3, and a bipolar transistor is formed on the single crystal silicon film 8.

4. 发明专利

JP2002083972A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002083972A
公开(公告)日：2002-03-22
申请号：JP2000274396
申请日：2000-09-11
申请人： HITACHI LTD
发明人： WAKAHARA YOSHIFUMI
IPC分类号： H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique by which a semiconductor integrated circuit device in which a MISFET is formed on the main surface of the so-called SOI substrate can be manufactured easily and, in addition, the potential at the substrate can be stabilized. SOLUTION: In the semiconductor integrated circuit device in which the MISFET is formed on the main surface of the SOI substrate, a thin silicon film (3) is formed so that a neutral area (10) may be formed in contact with a depletion layer (9) extended from the end sections of the source (4) and drain (5) of the MISFET and an insulating layer (8) is formed to face the gate electrode of the MISFET between the area of the silicon film (3) in which an inverted layer is formed when an electric field is applied across the source (4) and drain (5) of the MISFET and the neutral area (10).

5. 发明专利

JP2000183355A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000183355A
公开(公告)日：2000-06-30
申请号：JP36022498
申请日：1998-12-18
申请人： HITACHI LTD
发明人： WAKAHARA YOSHIFUMI , TAMAOKI YOICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technology for speeding up a semiconductor integrated circuit device which has a MISFET formed on an SOI substrate and improving reliability. SOLUTION: A groove, which is surrounded by a side wall spacer 11 and whose depth (d) is about 90-100 nm is formed on a polycrystalline silicon film 6, constituting the gate electrode of a MISFET. Silicons 13a and 13b with a thickness of about 100 nm are stacked on the surface of the exposed thin-film silicon layer 3. Thereafter, a titanium silicide layer is formed on the surfaces of the silicons 13a and 13b through self-matching.

6. 发明专利

JPH1056088A FERROELECTRIC MEMORY ELEMENT AND FERROELECTRIC MEMORY DEVICE EQUIPPED WITH IT 失效
公开(公告)号：JPH1056088A
公开(公告)日：1998-02-24
申请号：JP21148696
申请日：1996-08-09
申请人： HITACHI LTD
发明人： SHIGENIWA MASAHIRO , WAKAHARA YOSHIFUMI , SHOJI KENICHI , TORII KAZUNARI , HIRATANI MASAHIKO , KAWAHARA TAKAYUKI
IPC分类号： H01L21/8247 , G11C11/22 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To obtain a 1 Tr-type ferroelectric non-volatile memory which is kept almost free from problems related to material and processes and the influence of 21 leakage current from the viewpoint of the principle of operation and enhanced in degree of integration. SOLUTION: A pair of current input/output electrodes 4 and 5 are mounted on a semiconductor ferroelectric film 19. A pair of control electrodes 7 and 20 used for applying a voltage are provided to, at least, a part of the ferroelectric film 19 which serves as a current path. A depletion layer is formed in the semiconductor ferroelectric film 19 using one of the control electrodes 7 and 20 as a Schottky electrode 20. A ferroelectric memory element is formed in this constitution. A voltage is applied to the control electrodes 7 and 20 to induce polarization in the ferroelectric film 19. Different even polarization can be induced depending on the polarity of an applied voltage, and even polarization and uneven polarization are defined as memory data '0' and '1'. Memory data '0' and '1' are read out through a change in current conductance between the current input/output electrodes 4 and 5 based on the uniformity of polarization.

7. 发明专利

JP2002026313A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002026313A
公开(公告)日：2002-01-25
申请号：JP2000204929
申请日：2000-07-06
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , ICHINOSE KATSUHIKO , WAKAHARA YOSHIFUMI
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/772 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a technology for realizing fast operation of an MISFET of 0.15 μm or later generation. SOLUTION: With a gate electrode 10n and a side wall spacer 15 as masks, n-type impurity is ion-implanted in the normal direction of a substrate 1 to form a source/drain diffusion region 11b. Then an n-type impurity is ion- implanted by oblique implanting at a specified angle against the normal direction of the substrate 1, so that an n-type semiconductor region 16 is formed at a position 20-40 nm deep from the surface of substrate 1 whose impurity concentration is higher relative to a source/drain diffusion region 11a.

8. 发明专利

JPH11330473A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11330473A
公开(公告)日：1999-11-30
申请号：JP12839398
申请日：1998-05-12
申请人： HITACHI LTD
发明人： MITANI SHINICHIRO , WAKAHARA YOSHIFUMI , TAMAOKI YOICHI
IPC分类号： H01L27/08 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique which is capable of materializing the high- speed operation of a MISFET made on an SOI board, and prevent the operational failures of the MISFET. SOLUTION: The depletion layer of an n -type semiconductor region 6 and the depletion layer of a p -type semiconductor region 14 are in zero bias contact with an embedded insulating film 2 at all times, by providing this device with a film silicon layer 3 where impurities in low concentration of about 10 cm are implanted between an n -type semiconductor region 6 and an embedded insulating film 2 and between a p -type semiconductor region 14 and the embedded insulating film 2, so that the operation speed of a MISFET can be raised by suppressing the parasitic capacitance low. At the same time, it becomes possible to made the film silicon layer 3 thickness large, and the film silicon layer 3 is provided under an insulating film 4 for element isolation, so that the potential of the film silicon layer 3 can be fixed, and the operation failure of the MISFET caused by potential ripples can be prevented.

9. 发明专利

JPH1154758A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1154758A
公开(公告)日：1999-02-26
申请号：JP20749097
申请日：1997-08-01
申请人： HITACHI LTD
发明人： WAKAHARA YOSHIFUMI , TAMAOKI YOICHI
IPC分类号： H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To enable carriers of reverse polarity generated by impact ionization and staying in a channel region to flow away completely from a MISFET region. SOLUTION: An N-channel MISFET Qn and a P-channel MISFET Qp are formed on an SOI substrate 1 composed of a support substrate 1a, a buried oxide layer 1b, and a silicon layer 1c, a field insulating film 2a is formed on the main surface of the silicon layer 1c so as to reach the buried oxide layer 1b, a field insulating film 2b is formed on the main surface of the silicon layer 1c so as not to reach the oxide layer 1b, and an impurity semiconductor region 14 acting as a back gate is provided to the support substrate 1a which includes an interface region between the buried oxide layer 1b under the field insulating film 2b and the support substrate 1a. The impurity semiconductor region 14 is connected to a back gate electrode 12d formed in an connection hole 11d bored in the interlayer insulating film 10, the field insulating film 2a, and the buried oxide layer 1b, and a negative potential is applied to the semiconductor region 14.

10. 发明专利

JPH10189978A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10189978A
公开(公告)日：1998-07-21
申请号：JP34176696
申请日：1996-12-20
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , IKEDA TAKAHIDE , WAKAHARA YOSHIFUMI , HORIUCHI KATSUTADA , HIGUCHI HISAYUKI
IPC分类号： H01L27/08 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique which improves reliability of a semiconductor integrated circuit device with an MISFET, formed in an SOI board. SOLUTION: A 0.05 to 0.2μm-thick thin film silicon layer 3 with an impurity concentration of 10 /cm or more is formed between an LOCOS oxide film 4 and a embedded oxide film 2. Since minority carriers generated in a channel region thereby diffuse through the thin-film silicon layer 3 below the LOCOS oxide film 4, change in a threshold voltage of an MISFET by storage of the minority carriers can be restrained.

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