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1. 发明专利

JP2002231941A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002231941A
公开(公告)日：2002-08-16
申请号：JP2001030120
申请日：2001-02-06
申请人： HITACHI LTD
发明人： MITANI SHINICHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To reduce the capacitance between the source or drain and the gate electrode while reducing the resistance of the source and drain region. SOLUTION: Between the gate electrode G formed between the source and the drain (6) on a semiconductor substrate 1 via a gate insulation film and an extraction electrode section 9 formed on the source or drain (6), a space 11 is formed. Consequently, the resistance of the source and the drain region 6 can be reduced by the extraction electrode section 9 formed on the source or drain (6). The capacitance between the source or drain (6) and the gate electrode G can also be reduced by the gap 11 formed between the gate electrode G and the extraction electrode section 9.

2. 发明专利

JP2001077361A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001077361A
公开(公告)日：2001-03-23
申请号：JP25398699
申请日：1999-09-08
申请人： HITACHI LTD
发明人： MIYAMOTO MASABUMI , NONAKA YUSUKE , MITANI SHINICHIRO , YANAGISAWA YASUNOBU , SAITO TOMOHIRO
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To reduce the junction capacity of source/drain regions and to realize a high speed device operation by introducing the impurity of a conduction type opposite to a semiconductor substrate by oblique ion implantation and forming a counter dope layer by bringing it into contact with the lower par of a low concentration semiconductor region. SOLUTION: In an n-channel-type MISFETQ1, a p-type counter dope layer 8 whose impurity concentration is substantially low is formed below a low concentration semiconductor region 3 by oblique ion implantation. Thus, the junction capacity of the low concentration semiconductor region 3 can be reduced. The lateral invasion distance of a side wall spacer 7 from a spacer end to a channel direction can be adjusted at the angle of oblique ion implantation. Junction capacity between the low concentration semiconductor region 3 and the semiconductor substrate 1 can be reduced in a range that does not affect the short channel characteristics and therefore a high speed device operation can be executed.

3. 发明专利

JP2000196070A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000196070A
公开(公告)日：2000-07-14
申请号：JP36674398
申请日：1998-12-24
申请人： HITACHI LTD
发明人： NONAKA YUSUKE , MITANI SHINICHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To make an element minute, without affecting the properties of a MISFET, and suppress increase in parasitic resistance of the element accompanying micronization, and also obtain shallow joining of the semiconductor regions to serve as the source and the drain. SOLUTION: The gate electrode 7 is made via a gate insulating film 6 on the element formation region of the main surface of a p-type semiconductor substrate 1, and then semiconductor regions to serve as the source and the drain are made, self-alignedly to the gate electrode, in the element-forming regions of the substrate. Next, an insulating film is made on the element-forming region at the main face of the substrate and on an element isolating region, and the insulting film 11 is left on the element isolating region through selective anisotropic etching, and also a sidewall spacer A, on the sidewall of the gate electrode 7, and a connection hole 11B, on the semiconductor region, are made. Moreover, a conductive film 16 which is lower in sheet resistance than the semiconductor region is made on the main face of the semiconductor substrate including the connection hole, and then the insulating film in other region excluding the inside of the connection hole is removed.

4. 发明专利

JPH10340993A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效
公开(公告)号：JPH10340993A
公开(公告)日：1998-12-22
申请号：JP14893397
申请日：1997-06-06
申请人： HITACHI LTD
发明人： MIYAZAKI SUKEYUKI , MATSUZAKI NOZOMI , SHOJI KENICHI , MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , HIROSE KENJI , MITANI SHINICHIRO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To enable stable supply of a power supply voltage and simplification of design, by adjacently arranging a first wiring and a second wiring via insulator, dividing the second wiring into a plurality of parts, using the first wiring as a power supply line, and using the second wiring as a ground line. SOLUTION: First wiring metal 10 is covered with insulator 30. The outer periphery of the insulator is covered with second wiring metal 20. Wiring constituting the three-layered structure is inserted into a normal permitivity insulator film 40. The second wiring metal 20 and the insulator 30 are partly divided to the first wiring metal 10, and a plurality of parts exist. The wiring 10 is used as a wiring for power supply. One part of the wiring 20 is used as a ground line, and the other part is connected with the wiring 10. By using normal permittivity insulator or high permittivity insulator as the insulator 30, a capacitance is constituted between the wiring 10 and the wiring 20, so that stable power supply is enabled to the change of a voltage. Since the ground line 20 can be formed at a free position, the degree of freedom of wiring design is increased.

5. 发明专利

JPH09246382A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09246382A
公开(公告)日：1997-09-19
申请号：JP5631796
申请日：1996-03-13
申请人： HITACHI LTD
发明人： MITANI SHINICHIRO
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To enhance a semiconductor integrated circuit in degree of integration and performance. SOLUTION: A conductive layer 7 is formed on source/drain regions 5 through a selective CVD method in a self-aligned manner respectively, and the upside and side of a gate electrode 4 are covered with a first insulating layer 6 formed of material different from that of a second insulating layer 8 which serves as an interlayer insulating film. A contact hole 10a on the source/drain region 5 and a contact hole 10b on a gate electrode 4 in an isolation region 2 are etched at the same time, and a first insulating layer 6 is left on a gate electrode 4. In succession, the first insulating layer 6 left on the gate electrode 4 is etched using a resist provided with an opening corresponding to the contact hole 10b of the gate electrode 4 as a mask.

6. 发明专利

JPH09129743A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09129743A
公开(公告)日：1997-05-16
申请号：JP28485895
申请日：1995-11-01
申请人： HITACHI LTD
发明人： NONAKA YUSUKE , MITANI SHINICHIRO
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a logic circuit party which can perform high-speed operation, and a logic circuit part excellent in soft-error resistance on the same chip. SOLUTION: On the main surface of a semiconductor substrate 1, a low- concentration P-type well 2 and a low-concentration N-type well 3, wherein the profile of impurity concentration in the depth direction is uniform, are formed. A high-concentration P-type well 4 and a high-concentration N-type well 5 and also a p-type-element separating semiconductor region 7 and an N-type-element separating semiconductor region 8, wherein the maximum value is provided at the profile of the impurity concentration in the depth direction, are formed at the same time so that the impurity concentration becomes the maximum value (peak) at a part directly beneath a field insulating film 6. At this time, the low-concentration well region is utilized as a logic circuit part, and the high-concentration well region is utilized as a memory circuit part.

7. 发明专利

JPH06244196A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06244196A
公开(公告)日：1994-09-02
申请号：JP2950993
申请日：1993-02-19
申请人： HITACHI LTD
发明人： ICHINOSE KATSUHIKO , MITANI SHINICHIRO , OTSUKA FUMIO
IPC分类号： H01L21/8238 , H01L21/336 , H01L27/092 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a short-channel MISFET provided with improved current driving performance. CONSTITUTION:The pocket area 8A of an N-channel type MISFETQn is formed shallower than an N -type semiconductor area 7 and the pocket area 8B of a P-type MISFETQp is formed shallower than a P -type semiconductor area 15. Thus, impurities in the pocket areas are suppressed from diffusing to the bottom of a gate electrode and junction capacitance increase due to the pocket areas 8A and 8B is prevented.

8. 发明专利

JPH05167025A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05167025A
公开(公告)日：1993-07-02
申请号：JP33542391
申请日：1991-12-19
申请人： HITACHI LTD
发明人： MITANI SHINICHIRO , IKEDA TAKAHIDE , YAMADA KOICHIRO , KIKUSHIMA KENICHI , KAWAGUCHI ETSUKO , YOSHIDA MASAAKI , YOSHIDA EIICHI
IPC分类号： H01L27/06 , H01L21/8249
摘要： PURPOSE:To realize a high-integration and high-speed bipolar CMOS LSI by a method wherein the inhibition of the short-channel effect of a MISFET and a reduction in the junction capacity of the MISFET are made compatible with each other. CONSTITUTION:A bipolar CMOS LSI is formed into a structure, wherein an impurity concentration of an N-type well 5a constituting a collector region of an N-P-N bipolar transistor Q1 and an impurity concentration of an N-type well 5b of a P-channel MISFET Q2 formation region are respectively set at a low concentration and an N-type high impurity concentration semiconductor region 15 is formed under the lower part of a channel region 14a of the P- channel MISFET Q2 formation region in such a way that the depth of the peak concentration of its impurity concentration is smaller than that of the junction between a source and a drain of the Q2 formation region.

9. 发明专利

JPH0488666A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0488666A
公开(公告)日：1992-03-23
申请号：JP20324990
申请日：1990-07-31
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SHIMOYAMA MANABU , WATANABE TOKUO , IKEDA TAKAHIDE , KOIZUMI TORU , MITANI SHINICHIRO , KIKUSHIMA KENICHI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
摘要： PURPOSE:To enable a bipolar CMOS LSI to be simplified in manufacturing process, improved in reliability, and made to operate at a higher speed by a method wherein the base lead-out electrode of a bipolar transistor and the gate electrode of a MISFET are formed of the same conductive film at a time. CONSTITUTION:An insulating film 15, a high melting point metal silicide film 11, and a polycrystalline silicon film 10 are continuously etched through an anisotropic etching method, and a gate electrode 21 and a pace lead-out electrode 9 are formed at the same time. That is, gate electrodes 21 of MISFETs Q2 and Q3 and a base lead-out electrode 9 of a bipolar transistor Q1 are formed of the same conductive films (high melting point metal silicide film 11 and polycrystalline silicon film 10) of the same conductivity type (P -type) at the same time. By this setup, the manufacturing process of a bipolar CMOS LSI can be simplified, and an insulating film is provided under the electrode 9, whereby a bipolar transistor can be improved in reliability. A polycrystalline silicon film is filled into a gap under the electrode 9, whereby a bipolar transistor can be made to operate at a higher speed.

10. 发明专利

JPH0237105B2 失效
公开(公告)号：JPH0237105B2
公开(公告)日：1990-08-22
申请号：JP7535482
申请日：1982-05-07
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , MITANI SHINICHIRO
IPC分类号： H01L21/8238 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L27/02 , H01L27/092 , H01L29/78

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