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    • 46. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • JPH06291338A
    • 1994-10-18
    • JP10181893
    • 1993-04-06
    • CITIZEN WATCH CO LTD
    • SAKURAI YASUHIRO
    • H01L29/417H01L29/861H01L29/91H01L29/50
    • PURPOSE:To manufacture a semiconductor integrated circuit having a built-in rectifier circuit for obtaining a still more small-sized portable apparatus by using a single crystal or a crystalline film in proportion to a single-crystal and using a pn junction diode formed so as to locate at least the pn junction face on an insulating film for a rectifier circuit. CONSTITUTION:A p-type region, where a single-crystal film 5 of a single-ceystal is provided on one part on an insulating film 3 covering the surface of a semiconductor substrate 1 and an impurity such as boron is diffused on one part of this single-crystal film 5, and an n-type region, where an impurity such as phosphor is diffused on the other part of the single-crystal film 5 are provided for being made a pn junction diode. Since the pn junction diode is formed on the insulating film 3 so as to keep it away from the semiconductor substrate 1 to become a collector, abnormal operations are not generated even if it is used in the forward direction so as to enable it to be built-in in a semiconductor integrated circuit device. Next, as to a characteristic in the backward direction, a leakage current in the backward direction can be minimized because the pn junction diode is formed on the single-crystal film 5.
    • 47. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPH0697201A
    • 1994-04-08
    • JP24388092
    • 1992-09-14
    • TOSHIBA CORP
    • WAKAMATSU SHUICHI
    • H01L21/302H01L21/3065H01L21/338H01L29/417H01L29/812H01L29/50
    • PURPOSE:To form a gate electrode having excellent dimensional accuracy without using photoresist by utilizing the difference in etching rates in formation of an aperture part on a plasma nitride film deposited at low and high temperatures. CONSTITUTION:An optical CVD nitride film is deposited on the CVD oxide film 12 of a GaAs substrate 11 at the temperature of 100 deg.C or lower, and a nitride film 13 is formed by conducting a lift-off treatment. After a plasma nitride film 14 has been deposited at 300 deg.C, a dry-etching treatment 15 is conducted as deep as to the nitride film 13. The oxide film 12 is etched from the aperture part 14 of the nitride film 14, and a recess 16 is formed. Then, after Al has been vacuum-deposited as gate electrode metal, a passivation plasma nitride film is deposited at 300 deg.C. The gate electrode part is covered by a photoresist, and other nitride film is removed by dry etching. Besides, after the Al and the nitride film have been removed successively using the photoresit as a mask, the photoresist is removed, and a gate electrode is completed. It has an excellent dimensional accuracy and has no organic contamination by the electrode and the resit in the photoresist.
    • 48. 发明专利
    • JPH05267356A
    • 1993-10-15
    • JP6499292
    • 1992-03-23
    • H01L21/302H01L21/3065H01L21/3205H01L21/339H01L29/417H01L29/762H01L29/50H01L29/796
    • PURPOSE:To provide a semiconductor device having an even electrode film which does not allow a first electrode film to overlap with a second electrode film and its manufacturing method. CONSTITUTION:This manufacturing method comprises a process which forms a first electrode film 8 in the upper part of a semiconductor substrate, a process which thermally oxidizes the first electrode film 8, and forms a first oxide film 5a on the side of the first electrode film 8 and a second oxide film 5b in the upper part of the film, a process which forms a second electrode material film 4 all over the entire upper part, a process which polishes only the second electrode film 4 on the second oxide film 5b, using a polishing difference between the second oxide film 5b and the second electrode material film 4 and a process which patterns the second electrode material film 4 and thereby forms a second electrode film 9 (polysilicon film).
    • 49. 发明专利
    • JPH05235056A
    • 1993-09-10
    • JP3366492
    • 1992-02-20
    • FUJITSU LTD
    • SUEHIRO HARUHIKO
    • H01L21/302H01L21/3065H01L21/338H01L29/417H01L29/778H01L29/812H01L29/50
    • PURPOSE:To make low a parasitic resistance and to facilitate the control of a thershold value in regard to a semiconductor device, which is formed by a heterojunction and utilizes two-dimensional electron (hole) gas, and a method of manufacturing the device specially. CONSTITUTION:A method of manufacturing a semiconductor device has a process for growing in order a first compound semiconductor layer 3 to form a channel and a second compound semiconductor layer 4 to form a source and a drain on semiconductor substrates 1 and 2, a process for forming an insulating layer 5 on the layer 4 and a process, in which the layers 5 and 4 are etched and removed using a mask and an opening 7 for making the layer 3 expose is formed, and moreover, has a process for forming respectively insulative film (SiOQ film) sidewalls 8 on the side surfaces of the layer 4 in the opening 7, a process for growing a third compound semiconductor layer 9, which becomes an electron feeding layer, on the exposed layer 3 and a process for depositing a conductor layer 10 to form a gate electrode on the layer 9. In such the method, the semiconductor device is constituted.