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    • 2. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • JPH06216401A
    • 1994-08-05
    • JP745993
    • 1993-01-20
    • HITACHI LTDHITACHI MICOM SYST KK
    • WATANABE MASASHI
    • H01L27/082H01L21/331H01L21/8222H01L29/417H01L29/73H01L29/732H01L29/861H01L29/91H01L29/50
    • PURPOSE:To prevent the operation of a parasitic transistor resulting from the reverse breakdown strength of a diode element in a semiconductor integrated circuit device with a diode element formed by utilizing a lateral type bipolar transistor. CONSTITUTION:In a semiconductor integrated circuit, a P type semiconductor region 7 is arranged in a region, in which an anode wiring 11 is avoided, while a cathode wiring 12 is disposed on a main surface between the P type semiconductor region 8 of an N type epitaxial layer 2 and the P type semiconductor region 7 through an insulating film 5. A P type semiconductor region 4 is arranged on the main surface section of the N type epitaxial layer 2 on the outer circumferential surface of a diode element, and the anode wiring 11 is distributed on the main surface of the N type epitaxial layer 2 through the insulating film 5 between the P type semiconductor region 8 and the P type semiconductor region 4. An N type semiconductor region 6 having the same conductivity type as the N type epitaxial layer 2 and higher impurity concentration than the layer 2 is disposed under the anode wiring 11 of the main surface section of the N type epitaxial layer 2 between the P type semiconductor region 8 and the P semiconductor region 4.
    • 3. 发明专利
    • JPH05235045A
    • 1993-09-10
    • JP3335492
    • 1992-02-20
    • MITSUBISHI ELECTRIC CORP
    • KONO YASUTAKA
    • H01L29/417H01L21/338H01L29/812H01L29/50
    • PURPOSE:To obtain a high-performance field-effect transistor having high gate breakdown strength characteristics by a method wherein a silicon oxide insulating film is formed between an isolation layer formed by an ion implantation and a gate electrode. CONSTITUTION:A semiconductor layer 6 is formed on a compound semiconductor substrate and a recess 3 is formed in a gate electrode 1 formation place of the layer 6. A silicon oxide insulating film 5 is formed on the layer 6 comprising the recess 3 and the film 5 other than the film 5 on the gate electrode 1 formation place is removed by dry etching. Then, the place under the removed film 5 is patterned and an isolation layer 4 is formed by an ion implantation of boron in the periphery of a resist pattern excluding the gate electrode 1 formation place. By providing the film 5 having a high breakdown voltage between a gate electrode 1 and the layer 4 in such a way, a dielectric strength between the gate electrode over the layer 5 and a drain electrode can be improved.