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41. 发明专利

JP2005286334A TRENCH CAPACITOR USING SiGe AND ITS FORMING METHOD 有权
标题翻译：使用SiGe的TRENCH电容器及其形成方法
公开(公告)号：JP2005286334A
公开(公告)日：2005-10-13
申请号：JP2005092420
申请日：2005-03-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG SUK-JIN , LEE SEUNG-HWAN , KIM SUNGTAE , KIM YOUNG SUN , LIM JAE-SOON , PARK YOUNG-GEUN
IPC分类号： H01L27/108 , H01L21/334 , H01L21/82 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To provide a trench capacitor using SiGe and its forming method. SOLUTION: The method for forming the trench capacitor has step for: forming an etching mask having a first layer, a second layer, and an opening portion on a silicon substrate; forming a first trench by etching the second layer and the first layer using the etching mask; then, forming a recessed groove in the first layer by isotropicall etching the first layer selectively after forming an insulating film on the resultant product including the recessed groove; forming an insulating film collar in the recessed groove by anisotropically dry-etching the insulating film, etching the silicon substrate using the etching mask; forming a second trench by extending the first trench after removing the etching mask; forming a buried plate which covers the outside of the second trench; forming a dielectric film on the inner wall of the second trench; and forming a storing electrode. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供使用SiGe的沟槽电容器及其形成方法。解决方案：用于形成沟槽电容器的方法具有以下步骤：在硅衬底上形成具有第一层，第二层和开口部分的蚀刻掩模; 通过使用所述蚀刻掩模蚀刻所述第二层和所述第一层来形成第一沟槽; 然后，在包含所述凹槽的所得产品上形成绝缘膜之后，通过等温蚀刻所述第一层选择性地在所述第一层中形成凹槽; 通过对所述绝缘膜进行各向异性干蚀刻，在所述凹槽中形成绝缘膜套环，使用所述蚀刻掩模蚀刻所述硅衬底; 通过在移除蚀刻掩模之后延伸第一沟槽来形成第二沟槽; 形成覆盖第二沟槽外侧的掩埋板; 在所述第二沟槽的内壁上形成介电膜; 并形成存储电极。版权所有（C）2006，JPO＆NCIPI

42. 发明专利

JP2004274063A Method of forming bit line contact on vertical transistor of dram device using line forming master mask 有权
公开(公告)号：JP2004274063A
公开(公告)日：2004-09-30
申请号：JP2004064681
申请日：2004-03-08
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： YANG HAINING , RAMACHANDRA DEIBAKARUNI
IPC分类号： H01L27/10 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10841 , H01L29/66181
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a single bit line contact on a vertical transistor of a DRAM/e-DRAM device using a line forming master mask.
SOLUTION: By forming a patterning mask on the device with the line forming master mask, the part of the top surface of a gate electrode 100 is exposed on the top surface of a substrate. A divot reaching in the gate electrode alongside with a side wall spacer 300 juxtaposed with a source region 130 is etched, and filled with a dielectric material. A word line WL having a silicon nitride cap 220 is formed to be contacted with a gate electrode 100. An etching resistant conformal liner 230 is formed, and an ILD layer and a glass layer are formed. A bit line contact mask is formed to be patterned with the line forming master mask. A via hole BCV is etched to be juxtaposed with the side wall spacer 300 and reach to the source region 130, and the bit line contact is formed.
COPYRIGHT: (C)2004,JPO&NCIPI

43. 发明专利

JP2004514277A Method of manufacturing a trench capacitor 有权
公开(公告)号：JP2004514277A
公开(公告)日：2004-05-13
申请号：JP2002541723
申请日：2001-11-02
申请人：インフィネオンテクノロジーズアクチエンゲゼルシャフト
发明人：ゴールドバッハ，マティアス , ビルナー，アルベルト , フラノシュ，マルティン
IPC分类号： H01L21/3063 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087
摘要：本発明は、細孔（３−１２）を有するトレンチ（３−９）を備えるトレンチキャパシタの製造方法に関するものである。このトレンチキャパシタは、個々のキャパシタと集積半導体メモリとの双方に適している。メソ細孔は、トレンチキャパシタの電極のための表面を著しく上昇させ、これにより、トレンチキャパシタの容量を著しく上昇させる。本発明では、木食い虫が作るのと類似した小さなチャネルであり、２〜５０ｎｍの範囲の直径を有しているメソ細孔が、電気化学的に生成される。この方法により、高い容量対体積比率を有する容量を生成できる。本発明は、さらに、メソ細孔が、他のメソ細孔との、または、隣り合うトレンチとの最短距離に達すると、メソ細孔の成長が停止するという点で有利である（自己不活性化）。その結果、２つの隣り合うメソ細孔の間に短絡が生じることを、自己制御方法により防止できる。また、本発明は、本発明の方法を用いて生成できる半導体基板の正面側に、少なくとも１つのトレンチキャパシタを有している半導体装置にも関するものでもある。

44. 发明专利

JP2004111721A Semiconductor device and manufacturing method therefor 有权
公开(公告)号：JP2004111721A
公开(公告)日：2004-04-08
申请号：JP2002273409
申请日：2002-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： INO KAZUMI , ISHIUCHI HIDEMI , MATSUDA SATOSHI , SATO TSUTOMU , MIZUSHIMA ICHIRO
IPC分类号： H01L21/334 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8242 , H01L21/84 , H01L27/02 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/12 , H01L27/22 , H01L29/06 , H01L29/786
CPC分类号： H01L27/10894 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/0218 , H01L27/105 , H01L27/10829 , H01L27/1087 , H01L27/10885 , H01L27/10897 , H01L27/11 , H01L27/115 , H01L27/11502 , H01L27/1203 , H01L29/0649 , H01L29/66181 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, having a SON structure that can be made thin and to provide a manufacturing method of the device.
SOLUTION: The device is provided with the semiconductor substrate 10, plate-like hollows 11 formed in the semiconductor substrate 10 and element isolation regions 12 formed on a surface of the semiconductor substrate 10 so that they are brought into contact with end parts in the in-plane directions of the hollows 11.
COPYRIGHT: (C)2004,JPO

45. 发明专利

JP2004022642A Semiconductor device and method of manufacturing the same 审中-公开
公开(公告)号：JP2004022642A
公开(公告)日：2004-01-22
申请号：JP2002172629
申请日：2002-06-13
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI
IPC分类号： H01L27/108 , H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To prevent the epitaxial growth of an n-type polycrystalline silicon film connecting the storage node electrode of a trench capacitor to the n-type source/drain diffusion layer of an MOS (metal oxide semiconductor) transistor.
SOLUTION: At the time of connecting an n-type polycrystalline silicon film(storage node electrode) 12 through an n-type polycrystalline silicon film 15 to an n-type source/drain diffusion layer 23 of an MOS transistor, a WSiN layer 14 is interposed between the n-type polycrystalline silicon film 15 and the n-type source/drain diffusion layer 23.
COPYRIGHT: (C)2004,JPO

46. 发明专利

JP2003007856A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003007856A
公开(公告)日：2003-01-10
申请号：JP2001193323
申请日：2001-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： KOKUBU KOICHI
IPC分类号： H01L27/10 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/786 , H01L29/94
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10829 , H01L27/10894 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which p-well regions can be prevented from being turned to a floating state when trench capacitors are formed on a SOI substrate and stable operations of cell transistors can be ensured, and provide a manufacturing method thereof.
SOLUTION: The substrate 21-1 is connected to the p-well regions 21-2 by side-etching a buried oxide film 21-3 from the inside of each deep trench 22 and burying polysilicon or forming a conductive layer by an epitaxial growth. When the trench capacitors are formed on the SOI substrate, operations of cell transistors 26 can be made stable by preventing p-well regions 21-2 in which elements are formed from being turned to a floating state.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种半导体器件，其中当在SOI衬底上形成沟槽电容器时可以防止p阱区域变为浮置状态，并且可以确保单元晶体管的稳定操作，并提供制造方法其中。解决方案：通过从每个深沟槽22的内部侧蚀掩埋氧化膜21-3并且通过外延生长掩埋多晶硅或形成导电层，将衬底21-1连接到p阱区21-2。当在SOI衬底上形成沟槽电容器时，可以通过防止形成元件的p阱区21-2变为浮置状态来使单元晶体管26的工作变得稳定。

47. 发明专利

KR102235120B1 KR102235120B1 - Semiconductor device and method for method for fabricating the same 有权
公开(公告)号：KR102235120B1
公开(公告)日：2021-04-02
申请号：KR1020150093407A
申请日：2015-06-30
申请人： 삼성전자주식회사
发明人： 김은정 , 김봉수 , 김용관 , 한성희 , 황유상
IPC分类号： H01L27/108 , H01L21/764
CPC分类号： H01L27/108 , H01L21/764 , H01L27/10855 , H01L27/1087 , H01L27/10888 , H01L2924/1436
摘要： 반도체 소자 및 그의 제조 방법이 제공된다. 반도체 소자는 반도체 기판에 정의된 액티브 영역, 상기 반도체 기판 상에, 상기 액티브 영역과 연결되는 제1 콘택 플러그, 상기 반도체 기판 상에, 상기 제1 콘택 플러그와 인접하는 비트 라인, 상기 제1 콘택 플러그와 상기 비트 라인 사이에 형성된 제1 에어갭 스페이서, 상기 제1 콘택 플러그 상의 랜딩 패드, 상기 비트 라인 상의 블로킹 절연막으로, 상기 블로킹 절연막의 상면은 상기 랜딩 패드의 상면과 나란하거나 높은 블로킹 절연막 및 상기 제1 에어갭 스페이서 상에, 상기 제1 에어갭 스페이서와 수직적으로 중첩되고, 상기 블로킹 절연막 및 상기 랜딩 패드 사이에 위치하는 에어갭 캡핑막을 포함한다.

48. 发明专利

KR20210025893A KR20210025893A - DRAM Device Including an Air Gap and a Sealing layer and Method of Fabricating the Same 审中-公开
公开(公告)号：KR20210025893A
公开(公告)日：2021-03-10
申请号：KR1020190105873A
申请日：2019-08-28
申请人： 삼성전자주식회사
发明人： 강윤구 , 유원석 , 안호균 , 박경욱 , 이다인
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , G11C5/063 , G11C7/18 , H01L21/76816 , H01L21/7682 , H01L21/76829 , H01L21/76837 , H01L21/76852 , H01L27/10808 , H01L27/10835 , H01L27/10855 , H01L27/1087 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/0649
摘要： 에어 갭 및 씰링층을 갖는 디램 소자 및 그 제조 방법이 설명된다. 본 개시의 실시예들에 의한 씰링층은 제1 방향성 증착 공정을 이용하여 형성된 제1 씰링층 및 제2 방향성 증착 공정을 이용하여 형성된 제2 씰링층을 포함할 수 있다.

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